Channel strain engineering in field-effect-transistor
AssigneesInternational Business Machines Corporation, Infineon Technologies AG
InventorsThomas Dyer, Rajendran Krishnasamy, Jin-Ping Han, Ernst Demm
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Abstract
There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.
Claims19
A method of applying stress to a channel region underneath a gate of a field-effect-transistor, said field-effect-transistor (FET) including said gate, a source region, and a drain region, said method comprising:
- embedding stressors in said source and drain regions of said FET;
- forming a stress liner covering said gate of said FET and said source and drain regions;
- removing a portion of said stress liner, said portion of said stress liner being located on top of said gate, said gate being a gate conductor;
- removing said gate conductor of a first gate material and a layer of gate oxide underneath, thus creating an opening therein;
- and
- filling said opening with a second gate material.
A method of applying stress to a channel region underneath a gate of a field-effect-transistor, said field-effect-transistor (FET) including said gate, a source region, and a drain region, said method comprising:
- forming said gate of said FET with a gate material, said gate material having a Young's modulus value being smaller than 130 GPa, preferably smaller than 115 GPa, and more preferably smaller than 100 GPa;
- forming stressors at the two sides of said gate, said gate being a gate conductor and said stressors including a stress liner covering said gate and said source and drain regions of said FET;
- and
- removing said gate conductor of said gate material and a layer of gate oxide underneath, thereby creating an opening therein.
A method of applying stress to a channel region underneath a gate of a field-effect-transistor, said field-effect-transistor (FET) including said gate, a source region, and a drain region, said method comprising:
- embedding stressors in said source and drain regions of said FET;
- forming a stress liner covering said gate of said FET and said source and drain regions;
- removing a portion of said stress liner, said portion of said stress liner being located on top of said gate;
- removing said gate of a first gate material and a layer of a first gate oxide underneath, thus creating an opening therein;
- filling said opening with a layer of a second gate oxide;
- filling a second gate material on said layer of said second gate oxide;
- and
- removing said stress liner that covers said source and drain regions of said FET.
Dependencies are inferred from the claim text.