US 7,842,587 B2 · III-V MOSFET fabrication and device

Abstract

A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.

Claims13

Dependent claims

A semiconductor fabrication process, comprising:

forming, using molecular beam epitaxy, a gate dielectric layer overlying a wafer substrate, wherein the substrate includes at least one layer of a III-V semiconductor compound and wherein the gate dielectric layer includes a compound comprising an oxygen element and a second element wherein the second element is present in the III-V semiconductor compound;
patterning the gate dielectric layer to produce a gate dielectric structure having a substantially vertical sidewall;
forming a contact structure overlying said wafer substrate and laterally displaced from the gate dielectric structure, wherein the contact structure comprises at least one metal and wherein a lateral separation between the contact structure and the gate dielectric structure defines a gap;
heat treating the contact structure to produce an alloy region within the semiconductor substrate, wherein the alloy region underlies the contact structure and extends across a portion of the wafer substrate underlying the gap;
and
forming a capping layer overlying the wafer.

3 more elements

A method for fabricating a III-V MOSFET, comprising:

forming a compound semiconductor layer overlying a wafer substrate;
forming a gate dielectric layer overlying the compound semiconductor layer;
patterning the gate dielectric layer to produce a gate dielectric structure;
forming a contact structure comprising at least one metal element, the contact structure overlying the compound semiconductor layer and being laterally displaced from the gate dielectric structure sufficiently to define a gap between the contact structure and the gate dielectric structure;
forming an alloy region within the compound semiconductor layer by exposing the wafer to a heated ambient for a specified duration, wherein the alloy region includes at least some of the metal element and wherein the alloy region extends laterally through at least a portion of the compound semiconductor layer underlying the gap;
and
forming an insulating film overlying the wafer, wherein a lower surface of the insulating film is in contact with a portion of an upper surface of the compound semiconductor layer exposed by the gap;
wherein forming the insulating film comprises:
depositing, at a temperature of less than approximately 30° C., a first capping layer film of a first silicon nitrogen compound;
and
depositing, using chemical vapor deposition at a temperature of less than approximately 200° C., a second capping layer film of a second silicon-nitrogen compound.

8 more elements

Dependencies are inferred from the claim text.

III-V MOSFET fabrication and device

Life of this patent

III-V MOSFET fabrication and device

Life of this patent

Abstract

Claims13