Method for fabricating MOS devices with a salicided gate and source/drain combined with a non-silicide source drain regions

A method for fabricating an integrated circuit device, the method comprising:

• providing a semiconductor substrate, the semiconductor substrate comprising a first device region and a second device region;
• forming a trench isolation structure between the first device region and the second device region;
• forming a gate polysilicon layer overlying the first device region and the second device region;
• forming a silicide layer overlying the gate polysilicon layer;
• patterning the silicide layer and gate polysilicon layer to form a first silicided gate structure in the first device region and a second silicided gate structure in the second device region;
• forming a first sidewall spacer structure on the first silicided gate structure and a second sidewall spacer structure on the second silicided gate structure;
• forming a blocking layer overlying the second silicided gate structure and exposed portion of the second device region;
• forming a silicide material overlying a first source region and a first drain region associated with the first silicided gate structure;
• performing a single annealing process to form an alloy from at least the silicide material and the first silicided gate structure;
• maintaining a second source region and a second drain region associated with the second silicided gate structure free from any silicide using the blocking layer;
• and
• stripping the oxide blocking layer to expose the second source region and the second drain region to form a first transistor including the first silicided gate structure the silicided source first source region and the silicided first drain region and to-form a second transistor including the second silicided gate structure, the second silicide-free source region and the second silicide-free drain region;
• wherein the first transistor is an element of a digital processing circuit;
• wherein the second transistor is an element of an analog processing circuit.