Two-step STI formation process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorKa-Hing Fung
Life of this patent
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Abstract
A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.
Claims19
A method of forming an integrated circuit structure, the method comprising:
- providing a semiconductor substrate;
- forming a first isolation region in the semiconductor substrate;
- after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region;
- and
- after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate comprising:
- after the step of forming the source/drain region, etching a portion of the source/drain region away from a gate spacer of the MOS device to form a trench;
- and
- forming an inter-layer dielectric (ILD), wherein the ILD extends into the trench to form the second isolation region.
A method of forming an integrated circuit structure, the method comprising:
- providing a semiconductor substrate;
- forming a metal-oxide-semiconductor (MOS) device comprising:
- forming a gate stack on a top surface of the semiconductor substrate;
- forming a gate spacer on a sidewall of the gate stack;
- forming a source/drain region adjacent the gate spacer;
- and
- forming a silicide region on the source/drain region;
- etching a portion of the silicide region and a portion of the source/drain region to form a trench, wherein the trench is spaced apart from an outer edge of the gate spacer by a remaining portion of the source/drain region, and wherein the trench extends below a bottom of the source/drain region;
- and
- forming an inter-layer dielectric (ILD) over the MOS device, wherein the ILD extends into the trench to form a shallow trench isolation (STI) region.
A method of forming an integrated circuit structure, the method comprising:
- providing a semiconductor substrate;
- forming a first shallow trench isolation (STI) region in the semiconductor substrate, wherein the first STI region has a first lengthwise direction, and wherein the first STI region adjoins an active region;
- forming a first and a second gate electrode strip over the active region and the first STI region, wherein the first and the second gate electrode strips are parallel to each other;
- forming a common source/drain region in the active region and between the first and the second gate electrode strips;
- forming a silicide region on the common source/drain region;
- etching a portion of the silicide region and a portion of the common source/drain region to form a trench, wherein the trench has a second lengthwise direction parallel to the first and the second gate electrode strips;
- and
- forming an inter-layer dielectric (ILD) having a top surface higher than top surfaces of the first and the second gate electrode strips, wherein the ILD extends into the trench to form a second STI region.
Dependencies are inferred from the claim text.