Ultra thin package and fabrication method
AssigneeAmkor Technology, Inc.
InventorsSukianto Rusli, Ronald Patrick Huemoeller, Bob Shih-Wei Kuo, Lee John Smith
Life of this patent
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Abstract
A method includes forming a substrate layer, the substrate layer including a circuit pattern having terminals and bump pads. A stiffener is formed, the stiffener including via apertures having electrically conductive via aperture sidewalls and an electronic component opening. The stiffener is attached to the substrate layer. The electrically conductive via aperture sidewalls are electrically connected to the terminals. An electronic component is mounted to the bump pads and within the electronic component opening thus minimizing the height of the package. Further, the stiffener minimizing undesirable bending of the package and acts as an internal heat sink.
Claims19
A method of forming a partial cavity package comprising:
- forming a substrate layer, the substrate layer comprising a circuit pattern comprising terminals and bump pads;
- forming a stiffener, the stiffener comprising:
- via apertures comprising electrically conductive via aperture sidewalls;
- and
- an electronic component opening;
- attaching the stiffener to the substrate layer;
- electrically connecting the electrically conductive via aperture sidewalls to the terminals;
- and
- mounting an electronic component within the electronic component opening and electrically connected to the bump pads;
- and
- stacking a second electronic component on the electronic component.
A method of forming a partial cavity package comprising:
- forming a substrate layer comprising:
- coupling a first circuit pattern to a first surface of a dielectric layer;
- coupling a second circuit pattern to a second surface of the dielectric layer, the second circuit pattern comprising terminals and bump pads;
- and
- electrically connecting the first circuit pattern to the second circuit pattern with electrically conductive vias extending through the dielectric layer;
- forming a stiffener, the stiffener comprising:
- via apertures comprising electrically conductive via aperture sidewalls;
- and
- an electronic component opening;
- attaching the stiffener to the substrate layer;
- electrically connecting the electrically conductive via aperture sidewalls to the terminals;
- and
- mounting an electronic component within the electronic component opening and electrically connected to the bump pads.
A method of forming a partial cavity package comprising:
- forming a substrate layer, the substrate layer comprising a circuit pattern comprising terminals and bump pads;
- forming a stiffener, the stiffener comprising:
- via apertures comprising electrically conductive via aperture sidewalls;
- and
- an electronic component opening;
- attaching a first surface of the stiffener to the substrate layer;
- electrically connecting the electrically conductive via aperture sidewalls to the terminals;
- mounting an electronic component within the electronic component opening and electrically connected to the bump pads;
- encasing the electronic component in a package body, the package body filling the electronic component opening;
- attaching a first surface of a buildup layer to a second surface of the stiffener;
- forming vias in the buildup layer, the vias being electrically connected to stiffener terminals of the stiffener;
- and
- forming an outer circuit pattern coupled to a second surface of the buildup layer, the outer circuit pattern being electrically connected to the vias in the buildup layer.
A method of forming a partial cavity package comprising:
- forming a substrate layer, the substrate layer comprising a circuit pattern comprising terminals and bump pads;
- forming a stiffener, the stiffener comprising:
- via apertures comprising electrically conductive via aperture sidewalls;
- and
- an electronic component opening;
- attaching the stiffener to the substrate layer;
- electrically connecting the electrically conductive via aperture sidewalls to the terminals;
- and
- mounting an electronic component within the electronic component opening and electrically connected to the bump pads;
- encasing the electronic component in a package body, the package body filling the electronic component opening;
- forming vias in the package body electrically connected to through silicon vias of the electronic component;
- forming an outer circuit pattern coupled to a primary surface of the package body;
- and
- mounting a second electronic component to the outer circuit pattern.
A method of forming a partial cavity package comprising:
- forming a stiffener;
- forming stiffener terminals on the stiffener;
- attaching a buildup layer to the stiffener;
- patterning the buildup layer to form via apertures and an electronic component opening in the buildup layer, the via apertures exposing the stiffener terminals;
- filling the via apertures to form vias in the buildup layer electrically connected to the stiffener terminals;
- forming an outer circuit pattern coupled to the buildup layer and electrically connected to the vias in the buildup layer;
- mounting an electronic component to the stiffener and within the electronic component opening;
- and
- electrically connecting the electronic component to the outer circuit pattern.
A method of forming a partial cavity package comprising:
- forming a substrate layer;
- forming a stiffener;
- attaching the stiffener to the substrate layer;
- forming stiffener terminals on the stiffener;
- attaching a buildup layer to the stiffener;
- patterning the buildup layer to form via apertures and an electronic component opening in the buildup layer, the via apertures exposing the stiffener terminals;
- filling the via apertures to form vias in the buildup layer electrically connected to the stiffener terminals;
- forming an outer circuit pattern coupled to the buildup layer and electrically connected to the vias in the buildup layer;
- mounting an electronic component to the stiffener and within the electronic component opening;
- and
- electrically connecting the electronic component to the outer circuit pattern.
Dependencies are inferred from the claim text.