Edge exclusion zone patterning for solar cells and the like
AssigneePalo Alto Research Center Incorporated
InventorScott J. Limb
Life of this patent
Estimating the term…
Abstract
The edge profile (and optionally the physical and electrical characteristics) of a wafer is determined. Useful regions of the wafer in an edge exclusion zone may then be identified. A customized grid array layout is created specific to that wafer from an analysis of the edge profile, for example having a grid array with interconnection lines located within the useful portions of the edge exclusion zone. This working file is then used by a system, such as a digital lithography system, to form the grid array on the surface of the wafer. The grid array is specific to that wafer. Various aspects of the grid array may also be controlled in the process. For example, the line width, inter-line spacing, and position of the lines comprising the grid array are configurable on a wafer-by-wafer basis.
Claims19
A method for automatically patterning the surfaces of a plurality of wafers comprising:
- preparing a first wafer for patterning;
- measuring said first wafer to determine the characteristics of said first wafer in a region proximate the first wafer's edge;
- characterizing portions of said region proximate the first wafer's edge as either useful or not useful based upon said measuring;
- producing a first pattern layout of pattern features which includes features in portions of said region proximate the first wafer's edge characterized as useful and which does not include features in portions of said region proximate the first wafer's edge characterized as not useful;
- patterning said first wafer based on said first pattern layout;
- preparing a second wafer for patterning;
- measuring said second wafer to determine the characteristics of said second wafer in a region proximate the second wafer's edge;
- characterizing portions of said region proximate the second wafer's edge as either useful or not useful based upon said measuring;
- producing a second pattern layout of pattern features which includes features in portions of said region proximate the second wafer's edge characterized as useful and which does not include features in portions of said region proximate the second wafer's edge characterized as not useful;
- patterning said second wafer based on said second pattern layout;
- wherein said first pattern and said second pattern are different.
A method for automatically patterning the surface of a plurality of wafers, each wafer of a type having a wafer edge, comprising for at least a first and second of said wafers:
- preparing each said wafer for patterning;
- defining an edge exclusion zone proximate each wafer's edge;
- measuring the topography of each said edge exclusion zone and the locations of each said wafer edge relative to a fiducial point on each said wafer;
- characterizing portions of each said edge exclusion zone as either useful or not useful based upon said measuring;
- producing a first layout for said first wafer and a second layout for said second wafer, each layout comprising interconnection lines radially inward and not within each said edge exclusion zone of said first and second wafers, respectively;
- extending at least one of said first and second layouts of interconnection lines such that certain of said lines selectively extend within said edge exclusion zone in portions characterized as useful, said lines not extending within said edge exclusion zone in portions characterized as not useful for said at least one of said first and second wafers;
- and
- patterning said first and second wafers based on said first and second pattern layouts, respectively;
- wherein said first and second patterns are different.
A method for automatically patterning the surface of a plurality of wafers, each wafer of a type having a wafer edge, comprising for at least a first and second of said wafers:
- preparing each said wafer for patterning;
- defining an edge exclusion zone proximate each wafer's edge;
- measuring the topography of each said edge exclusion zone and the locations of each said wafer edge relative to a fiducial point on each said wafer;
- characterizing portions of each said edge exclusion zone as either useful or not useful based upon said measuring;
- producing a first layout for said first wafer and a second layout for said second wafer, each layout comprising interconnection lines radially inward and not within each said edge exclusion zone;
- adding to at least one of said first and second layout additional interconnection lines such that said additional interconnection lines are added only within said edge exclusion zone in portions characterized as useful for said at least one of said first and second wafers;
- and
- depositing on said first and second wafers by digital lithography, on a droplet-by-droplet basis, first and second masks used for patterning said first and second wafers, respectively;
- patterning said first and second wafers using said first and second masks;
- and
- removing said first and second masks;
- wherein said first and second patterns are different.
Dependencies are inferred from the claim text.