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US 7,839,707 B2Granted
Fuses for memory repair
AssigneeVitesse Semiconductor Corporation
InventorThomas Aakjer
Life of this patent
Estimating the term…
Abstract
Structures for fuses to control repair of multiple memories embedded on an integrated circuit are provided along with methods of use. A set of fuses is shared to control repair of a plurality of memories. Some of the fuses are associated with a memory to be repaired. Others of the fuses identify how the repair is accomplished.
Claims26
An integrated circuit, comprising:
- a plurality of memories each with a redundant section;
- a first set of permanent storage devices to identify one of the plurality of memories, and
- a second set of permanent storage devices to specify use of the redundant section of the memory identified by the first set of permanent storage devices.
An integrated circuit, comprising:
- a plurality of memories each with a redundant section;
- a first plurality of sets of permanent storage devices, one associated with each of the plurality of memories, storing data to conditionally enable use of the redundant section of the associated memory;
- circuitry sensing data programmed into the first sets of permanent storage devices to generate memory repair enable signals;
- a second plurality of sets of permanent storage devices, each specifying a redundancy utilization;
- circuitry sensing data programmed into the second sets of permanent storage devices to generate repair control signals;
- and
- multiplexers selecting one of the repair control signals based on the repair enable signals.
4 more elements
A process for programming fuses for repair of integrated circuit memories, comprising:
- testing memories in an integrated circuit;
- identifying a faulty memory;
- identifying a repair for the faulty memory;
- programming first permanent storage devices on the integrated circuit to signal the identified faulty memory;
- and
- programming second permanent storage devices on the integrated circuit to signal the identified repair for the faulty memory.
3 more elements
A process for repair of memories embedded in an integrated circuit, comprising:
- testing memories in an integrated circuit;
- identifying a faulty memory;
- identifying a repair for the faulty memory;
- programming a first set of permanent storage devices on the integrated circuit to signal the identified faulty memory;
- programming a second set of permanent storage devices on the integrated circuit to signal the identified repair,
- sensing the status programmed into the permanent storage devices;
- identifying a memory for repair from the sensed status;
- and
- repairing the identified memory based on the sensed status.
6 more elements
Dependencies are inferred from the claim text.