Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips
AssigneePowertech Technology Inc.
InventorMing-Yao Chen
Life of this patent
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AssigneePowertech Technology Inc.
InventorMing-Yao Chen
Estimating the term…
A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and second bonding pads. By forming first extruded ring, the first bonding pad has a first contact surface located between the first extruded ring and the through hole. By forming second extruded ring, the second bonding pad has a second contact surface located outside and adjacent to the second extruded rings to encircle the second extruded ring. The second extruded ring has a proper dimension to fit in the first extruded ring. Accordingly, a plurality of semiconductor chip can be stacked each other with accurate alignment without shifting to effectively reduce the stacked assembly height, moreover, chip stacking processes are accomplished by vertically stacking a plurality of chips first then filling conductive material into the through holes without electrical short between the adjacent bonding pads due to overflow of conductive material to meet the fine-pitch requirements of TSV. The process flow for the stacked assembly is simplified with higher production yields.
A semiconductor chip primarily comprising:
A stacked assembly comprising a plurality of semiconductor chips vertically stacked on each other and a carrier, each semiconductor chip comprising:
A semiconductor chip primarily comprising:
Dependencies are inferred from the claim text.