Specialized processing block for programmable logic device
AssigneeAltera Corporation
InventorsMartin Langhammer, Kwan Yee Martin Lee, Triet M. Nguyen, Keone Streicher, Orang Azgomi
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Abstract
A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.
Claims23
A specialized processing block for a programmable logic device, said specialized processing block comprising:
- a plurality of fundamental processing units, each of said fundamental processing units including:
- a plurality of multipliers, and
- circuitry for adding, in one operation, partial products produced by all of said plurality of multipliers;
- and
- circuitry interconnecting said fundamental processing units, said circuitry interconnecting said fundamental processing units comprising circuitry for selectably combining outputs of said plurality of multipliers of each of a plurality of said fundamental processing units for combined input to said circuitry for adding, whereby said circuitry for adding selectably adds, in said one operation, said partial products produced by all of said plurality of multipliers in each of said plurality of said fundamental processing units.
Dependencies are inferred from the claim text.