Resistive memory
AssigneeMicron Technology, Inc.
InventorsYantao Ma, Jun Liu
Life of this patent
Estimating the term…
Abstract
The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least one resistive memory element, a programming circuit, and a sensing circuit. For example, the programming circuit can include a switch configured to select one of N programming currents for programming the at least one resistive memory element, where each of the N programming currents has a unique combination of current direction and magnitude, with N corresponding to the number of resistance states of the at least one memory element. In one or more embodiments, the sensing circuit can be arranged for sensing of the N resistance states.
Claims37
A memory device, comprising
- at least one resistive memory element;
- a programming circuit including a switch configured to select one of N programming currents for programming the at least one resistive memory element, where each of the N programming currents has a unique combination of current direction and magnitude, with N corresponding to the number of resistance states of the at least one memory element;
- and
- a sensing circuit arranged for sensing of the N resistance states.
A memory device, comprising
- at least one memory cell coupled to an intermediate potential during operation of the memory cell including a resistive memory element and an access device;
- a programming circuit, including:
- a write switch having an output and a plurality of selectable inputs, the at least one memory cell coupled between the write switch output and the intermediate potential during operation of the programming circuit;
- one or more pairs of first transistors coupled between at least a first potential during operation of the programming circuit and at least one of the plurality of selectable write switch inputs;
- one or more pairs of second transistors coupled between at least a second potential during operation of the programming circuit and at least one of the plurality of selectable write switch inputs;
- and
- a sensing circuit, including:
- a cascode current mirror circuit having a reference current stage and at least one mirror current stage, the reference current stage being selectively coupled through a read switch to the at least one memory cell.
A method for operating a circuit, comprising:
- selecting an individual memory element of a resistive memory, the memory element being programmed to one of N resistance states, with N being an integer greater than one;
- and
- passing a sensing current through the memory element, the sensing current being a reference current of a current mirror circuit;
- generating N−1 mirror currents, the mirror currents being proportional to the reference current, each mirror current having a magnitude that is proportional to a magnitude of the reference current;
- and
- determining, in parallel, from each mirror current the particular one of the N resistance states to which the memory element is programmed.
Dependencies are inferred from the claim text.