Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits
AssigneeXilinx, Inc.
InventorsStephen M. Trimberger, Austin H. Lesea
Life of this patent
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Abstract
An integrated circuit is used to monitor and process parametric variations, such as temperature and voltage variations. An integrated circuit may include a temperature-sensitive oscillator circuit and a temperature-insensitive oscillator circuit, and frequency difference between the two sources may be monitored. In some embodiments, a parametric-insensitive reference oscillator is used as a reference to measure frequency performance of a second oscillator wherein the second oscillator performance is parametric-sensitive. The measured frequency performance is then compared to a tamper threshold and the result of the comparison is indicative of tampering.
Claims17
A method for detecting tampering in an Integrated circuit (IC) due to parametric shift comprising:
- supplying a reference signal, wherein the reference signal is insensitive to the parametric shift;
- supplying a sensitive signal, wherein the sensitive signal is sensitive to the parametric shift;
- measuring performance of the sensitive signal in reference to the reference signal;
- comparing the measured performance of the sensitive signal to a value, wherein the value represents a parametric shift tampering limit;
- generating a tamper signal in response to the step of comparing,
- wherein the parametric shift includes at least one of a temperature shift and a voltage shift;
- and
- powering down at least a portion of the IC in response to the tamper signal.
A method of configuring a programmable logic device (PLD) to detect a parametric shift comprising:
- configuring the PLD to include a core oscillator, wherein performance of the core oscillator is sensitive to the parametric shift;
- enabling a clock manager circuit of the PLD receiving a reference oscillator, wherein performance of the reference oscillator is insensitive to the parametric shift;
- configuring the PLD to measure performance of the core oscillator in reference to the clock manager circuit;
- configuring the PLD to compare the measured performance of the core oscillator to a value, wherein the value represents a parametric shift tampering threshold;
- generating a tamper signal in response to comparing the measured performance of the core oscillator to the value, wherein the tamper signal is indicative of the parametric shift;
- and powering down at least a portion of the PLD in response to the tamper signal.
In an integrated circuit (IC), a circuit for detecting a parametric shift comprising:
- a parametric-insensitive clock circuit having a first clock output, wherein the first clock output is insensitive to the parametric shift;
- a parametric-sensitive clock circuit having a second clock output, wherein the second clock output is sensitive to the parametric shift;
- a counter circuit having a first counter input coupled to the first clock output, a second counter input coupled to the second clock output, and a counter output, wherein the counter output is responsive to counting the first clock output and the second clock output;
- a comparator circuit having a first comparator input coupled to the counter output, a second comparator input coupled to receive a parametric shift tampering threshold, and a comparator output, wherein the comparator output is a tamper signal that is generated in response to comparing the counter output to the parametric shift tampering threshold, and wherein the comparator output indicates a parametric shift;
- and
- a secure IP block having a first secure IP input coupled to the comparator output, wherein the secure IP block follows a security protocol in response to the tamper signal.
Dependencies are inferred from the claim text.