US 7,830,986 B1 · Method and apparatus for a phase/frequency locked loop

Abstract

A phase/frequency detector module allows operation as either a phase locked loop or a frequency locked loop. As a phased locked loop (PLL), the phase detector module is configured to decode phase differences between a reference signal and a voltage controlled oscillator (VCO) signal into phase correction signals that are updated at the rate of the VCO signal. An accumulation of the phase correction signals is implemented to form an accumulated phase error signal, which is then sampled at a lower rate than the VCO signal to accommodate slower components of the PLL, such as a digital to analog converter (DAC). As a frequency locked loop (FLL), the phase detector module is configured with frequency counters, so that frequency error may instead be detected. Any reduction of gain caused by the frequency counters is inherently equalized by the phase detector module.

Claims20

Dependent claims

A phase locked loop (PLL), comprising:

a phase detector coupled to receive first and second signals and adapted to provide an error signal indicative of a phase error between the first and second signals, the phase detector having a decoder coupled to receive first, second and third phase indication signals derived from the first signal being sampled by at least a first phase of the second signal and a second phase of the second signal to provide an incremental phase error and an accumulator adapted to accumulate the incremental phase error between the first and second signals, the incremental phase error being accumulated synchronously with the second signal, wherein the error signal is based upon the accumulated phase error;
a loop filter coupled to receive the error signal and adapted to provide a control signal in response to the error signal;
and
an oscillator coupled to receive the control signal and adapted to adjust a phase of the second signal to be substantially equal to a phase of the first signal in response to the control signal.

1 more element

A frequency locked loop (FLL), comprising:

a frequency detector coupled to receive first and second signals and adapted to provide an error signal indicative of a frequency error between the first and second signals, the frequency detector having:
one or more counter modules coupled to receive the first and second signals and adapted to generate first and second count signals, the first and second count signals being indicative of a frequency of the first signal and a frequency of a second signal, respectively;
a first circuit coupled to receive the first count signal and adapted to generate a first frequency indicator signal;
a second circuit coupled to receive the second count signal and adapted to generate a second frequency indicator signal;
and
a decoder coupled to receive first, second, and third phase indication signals derived from the first frequency indicator signal being sampled by at least a first phase of the second frequency indicator signal and a second phase of the second frequency indicator signal to provide an incremental phase error, wherein the error signal is based upon the incremental phase error;
a loop filter coupled to receive the error signal and adapted to provide a control signal in response to the error signal;
and
an oscillator coupled to receive the control signal and adapted to adjust the frequency of the second signal to be substantially equal to the frequency of the first signal in response to the control signal.

6 more elements

An integrated circuit (IC), comprising:

a frequency detector coupled to receive first and second signals and adapted to provide an error signal indicative of a frequency error between the first and second signals, the frequency detector comprising:
a counter coupled to receive the first and second signals and adapted to generate first and second count signals, the first and second count signals being indicative of a frequency of the first signal and a frequency of the second signal;
a first bit selector coupled to receive the first count signal and adapted to select one of a plurality of bits of the first count signal as a first frequency indicator signal;
a second bit selector coupled to receive the second count signal and adapted to select one of a plurality of bits of the second count signal as a second frequency indicator signal;
and
a decoder coupled to receive first, second, and third phase indication signals associated with the first frequency indicator signal and the second frequency indicator signal and adapted to provide first and second incremental phase error signals, wherein the error signal is based upon the first and second incremental phase error signals;
and
a loop filter coupled to receive the error signal and adapted to provide a control signal in response to the error signal, wherein the IC receives the second signal externally in response to providing the control signal externally.

5 more elements

Dependencies are inferred from the claim text.

Method and apparatus for a phase/frequency locked loop

Life of this patent

Method and apparatus for a phase/frequency locked loop

Life of this patent

Abstract

Claims20