Back to results
US 7,827,372 B2Granted
Intergrated circuit and a method of cache remapping
AssigneeNXP B.V.
InventorsAdrianus Josephus Bink, Paul Stravers
Life of this patent
Estimating the term…
Abstract
An integrated circuit is provided with at least one processing unit (TM), a cache memory (L2 BANK) having a plurality of memory modules, and remapping means (RM) for performing an unrestricted remapping within said plurality of memory modules. Accordingly, faulty modules can be remapped without limitations in order to optimise the utilization of the memory modules by providing an even distribution of the faulty modules.
Claims20
An integrated circuit, comprising:
- at least one processing unit (PU);
- a cache memory (L2_bank) having a plurality of memory modules for caching data, wherein the cache memory comprises a plurality of distinct physical banks, wherein each physical bank comprises some of the memory modules and is configured to facilitate serving a read/write request independently of other physical banks to allow concurrent transfers for at least two of the physical banks;
- and
- signal selection circuitry for identifying which memory modules have data cached in said cache memory wherein the signal selection circuitry comprises:
- a Tag RAM unit (TagRAM) to generate a hit signal based on an input address, wherein the hit signal is indicative of an originally mapped way for data corresponding to the input address;
- and
- remapping means (RM, MapRAM) for performing a remapping within said plurality of memory modules, wherein the remapping permits remapping the memory modules from a first physical bank of memory modules to a second physical bank of memory modules, wherein the remapping means is configured to generate a hit' signal based on the hit signal from the Tag RAM unit, wherein the hit' signal is indicative of a remapped way for the data corresponding to the input address.
4 more elements
A method of cache remapping in an integrated circuit having at least one processing unit (PU);
- a main memory (MM) for storing data;
- and a cache memory (L2_BANK) having a plurality of memory modules for caching data, the method comprising:
- generating a hit signal based on an input address, wherein the hit signal is indicative of an originally mapped way for data corresponding to the input address;
- performing a remapping within said plurality of memory modules wherein the memory modules are distributed among a plurality of distinct physical banks within the cache memory, and each physical bank is configured to facilitate serving a read/write request independently of the other physical banks to allow concurrent transfers for at least two of the physical banks, wherein the remapping permits remapping the memory modules from a first physical bank of memory modules to a second physical bank of memory modules;
- and
- generating a hit' signal based on the hit signal, wherein the hit' signal is indicative of a remapped way for the data corresponding to the input address.
3 more elements
Dependencies are inferred from the claim text.