Complex symbol evaluation for programmable intelligent search memory

The integrated circuit chip comprising programmable intelligent search memory for content search wherein said programmable intelligent search memory performs regular expression based search and wherein said regular expression comprises complex symbols, said programmable intelligent search memory for content search using one or more regular expressions, said one or more regular expressions comprising one or more symbols or characters and further comprising one or more complex symbols, said one or more regular expressions converted into one or more finite state automata representing the functionality of said one or more regular expressions for programming in said programmable intelligent search memory, said one or more finite state automata comprising a plurality of states, said plurality of states derived from said one or more symbols or characters of said one or more regular expressions, said content comprising one or more input symbols provided as input to said programmable intelligent search memory, said programmable intelligent search memory comprising at least one of each of:

• a. a symbol memory circuit to store said one or more symbols;
• b. a complex symbol memory circuit to store said one or more complex symbols;
• c. a complex symbol evaluation circuit coupled to said complex symbol memory circuit to evaluate match of said one or more complex symbols stored in said complex symbol memory circuit with said one or more input symbols of said content;
• d. a symbol evaluation circuit coupled to said symbol memory circuit to evaluate match of said one or more symbols stored in said symbol memory circuit with said one or more input symbols of said content;
• e. a state dependent vector memory circuit to store state transition controls for said one or more finite state automata;
• f. a current state vector memory circuit to store said plurality of states;
• and
• g. a state transition circuit coupled to said symbol evaluation circuit, said complex symbol evaluation circuit, said current state vector memory circuit and said state dependent vector memory circuit to perform state transition from one or more first states to one or more second states of said plurality of states of said one or more finite state automata.