Combined interpolation and decimation filter for programmable logic device

A method of programmably configuring a Finite Impulse Response (FIR) filter structure in a programmable logic device, said programmable logic device having at least one specialized processing block each of which includes a plurality of multipliers and circuitry for adding outputs of said multipliers, said method comprising:

• programmably configuring at least one said specialized processing block as a FIR filter structure;
• including:
• (1) programmably configuring said FIR filter structure with a number N of multipliers, where:
• N=INT [CT/(snSH)]+1 when MOD [CT/(snSH)]≠0,
• N=CT/(snSH) when MOD [CT/(snSH)]=0
• C=the number of channels,
• T=the number of taps,
• s=1 for an asymmetric filter,
• s=2 for a symmetric filter,
• n=the interpolation/decimation factor,
• S=a timesharing factor representing the number of clock cycles available to the system to process one input or output sample,
• H is a factor that represents whether the case is a fullband case (H=1) or a halfband case (H=2) in which all odd coefficients with the exception of the middle coefficient are zero,
• MOD [x]=x−INT[x], and
• INT[x] is the largest integer in x;
• (2) programmably configuring each of said N multipliers to have a sample input and a coefficient input, and programmably configuring said coefficient input to cycle through a plurality of coefficients;
• (3) programmably configuring at least one circuit for adding outputs of said multipliers to each other;
• (4) programmably configuring a respective selectable delay located at least one of (a) before, and (b) after, each said circuit for adding;
• and
• (5) programmably configuring said FIR filter structure to allow selection between an interpolation filter mode and a decimation filter mode during operation of said FIR filter structure;
• wherein:
• said selection comprises selection of at least one said respective selectable delay.

A data storage medium encoded with machine-executable instructions for performing a method of programmably configuring as a Finite Impulse Response (FIR) filter structure in a programmable logic device, said programmable logic device having at least one specialized processing block each of which includes a plurality of multipliers and circuitry for adding outputs of said multipliers, said instructions comprising:

• instructions for programmably configuring at least one said specialized processing block as a FIR filter structure;
• including:
• (1) instructions for programmably configuring said FIR filter structure with a number N of multipliers, where:
• N=INT [CT/(snSH)]+1 when MOD [CT/(snSH)]≠0, and
• N=CT/(snSH) when MOD [CT/(snSH)]=0
• C=the number of channels,
• T=the number of taps,
• s=1 for an asymmetric filter,
• s=2 for a symmetric filter,
• n=the interpolation/decimation factor,
• S=a timesharing factor representing the number of clock cycles available to the system to process one input or output sample,
• H is a factor that represents whether the case is a fullband case (H=1) or a halfband case (H=2) in which all odd coefficients with the exception of the middle coefficient are zero,
• MOD [x]=x−INT[x], and
• INT[x] is the largest integer in x;
• (2) instructions for programmably configuring each of said N multipliers to have a sample input and a coefficient input, and programmably configuring said coefficient input to cycle through a plurality of coefficients;
• (3) instructions for programmably configuring at least one circuit for adding outputs of said multipliers to each other;
• (4) instructions for programmably configuring a respective selectable delay located at least one of (a) before, and (b) after, each said circuit for adding;
• and
• (5) instructions for programmably configuring said FIR filter structure to allow selection between an interpolation filter mode and a decimation filter mode during operation of said FIR filter structure;
• wherein:
• said selection comprises selection of at least one said respective selectable delay.