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US 7,808,847 B2Granted
Memory repair circuit and repairable pseudo-dual port static random access memory
AssigneeOrise Technology Co., Ltd.
InventorsSzu-Mien Wang, Dan-Chi Yang
Life of this patent
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Abstract
The present invention relates to a memory repair circuit and a repairable pseudo-dual port static random access memory (pseudo-dual port SRAM). The memory repair circuit uses fewer redundant column blocks and stores a few failed block addresses to reduce the required complexity of decoding the redundant column blocks. Thus, the present invention can reduce a layout area required by redundant memory cells.
Claims10
A repairable pseudo-dual port static random access memory, comprising:
- a memory cell array comprising a plurality of memory cell blocks and a redundant block, wherein each of the memory cell blocks is divided into a plurality of memory cell sub-blocks, and a size of the redundant block is the same as a size of the memory cell sub-blocks;
- an address decoding circuit, comprising:
- a row address decoding circuit for turning on a specific row of the memory cell array according to the specific row specified by a row address;
- a first column address decoding circuit, having an N-bit connection bus, for electrically connecting N first specific columns of the memory cell array to the N-bit connection bus of the first column address decoding circuit according to the N first specific columns specified by a first column address signal, wherein N is a natural number;
- and
- a second column address decoding circuit, having an M-bit connection bus, for electrically connecting M second specific columns of the memory cell array to the M-bit connection bus of the second column address decoding circuit according to the M second specific columns specified by a second column address signal, wherein M is a natural number and greater than N;
- a first input-output port having an N-bit bus;
- a second input-output port having an M-bit bus;
- a first select circuit coupled to the N-bit connection bus of the first column address decoding circuit and the N-bit bus of the first input-output port, wherein when a first specific column specified by the first column address signal is in a failed memory cell sub-block, the first select circuit selects a first corresponding column of the redundant block, and connects the first corresponding column of the redundant block to the N-bit bus of the first input-output port, wherein a relative address of the first corresponding column is the same as an address of the first specific column in the failed memory cell sub-block;
- and
- a second select circuit coupled to the M-bit connection bus of the second column address decoding circuit and the M-bit bus of the second input-output port, wherein when a second specific column specified by the second column address signal is in the failed memory cell sub-block, the second select circuit selects a second corresponding column of the redundant block, and couples the second corresponding column of the redundant block to the M-bit bus of the second input-output port, wherein a relative address of the second corresponding column is the same as an address of the second specific column in the failed memory cell sub-block.
8 more elements
A repair circuit of a pseudo-dual port static random access memory, wherein the pseudo-dual port static random access memory comprises:
- a memory cell array comprising a plurality of memory cell blocks, wherein each of the memory cell blocks is divided into a plurality of memory cell sub-blocks;
- an address decoding circuit, comprising:
- a row address decoding circuit for turning on a specific row of the memory cell array according to the specific row specified by a row address;
- a first column address decoding circuit, having an N-bit connection bus, for electrically connecting N first specific columns of the memory cell array to the N-bit connection bus of the first column address decoding circuit according to the N first specific columns specified by a first column address signal, wherein N is a natural number;
- and
- a second column address decoding circuit, having an M-bit connection bus, for electrically connecting M second specific columns of the memory cell array to the M-bit connection bus of the second column address decoding circuit according to the M second specific columns specified by a second column address signal, wherein M is a natural number and greater than N;
- a first input-output port having an N-bit bus;
- and
- a second input-output port having an M-bit bus;
- and
- the memory repair circuit comprises:
- a redundant block disposed in the memory cell array, wherein a size of the redundant block is the same as a size of the memory cell sub-blocks;
- a first select circuit coupled to the N-bit connection bus of the first column address decoding circuit and the N-bit bus of the first input-output port, wherein when a first specific column specified by the first column address signal is in a failed memory cell sub-block, the first select circuit selects a first corresponding column of the redundant block, and connects the first corresponding column of the redundant block to the N-bit bus of the first input-output port, wherein a relative address of the first corresponding column is the same as an address of the first specific column in the failed memory cell sub-block;
- and
- a second select circuit coupled to the M-bit connection bus of the second column address decoding circuit and the M-bit bus of the second input-output port, wherein when a second specific column specified by the second column address signal is in the failed memory cell sub-block, the second select circuit selects a second corresponding column of the redundant block, and couples the second corresponding column of the redundant block to the M-bit bus of the second input-output port, wherein a relative address of the second corresponding column is the same as an address of the second specific column in the failed memory cell sub-block.
12 more elements
Dependencies are inferred from the claim text.