Frequency divider circuits

A circuit for deriving an output clock signal from an input clock signal, the output clock signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number, the circuit comprising:

• a plurality of latches configured as a latch ring, the latches being arranged in successive pairs, each pair of latches comprising a first latch that switches on one of the rising or falling edge of the input clock signal, and a second latch that switches on the other of the rising or falling edge of the input clock signal;
• and
• a memory element having set and reset inputs for setting and resetting an output of the element, the element being coupled to receive at one of its set and reset inputs an output from the latch ring that is switched on a rising edge of the input clock signal, and at the other of the set and reset inputs an output from the latch ring that is switched on a falling edge of the input clock signal,
• said output clock signal being provided at said output of the memory element.