Caching in multicore and multiprocessor architectures
AssigneeTilera Corporation
InventorsAnant Agarwal, Ian R. Bratt, Matthew Mattina
Life of this patent
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Abstract
A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some of the memory interfaces providing access paths to the main memory for multiple of the cache memories. Each of the memory interfaces is associated with a corresponding portion of the main memory, and includes a directory controller for the portion of the main memory.
Claims81
A multicore processor comprising:
- a plurality of cache memories;
- a plurality of processor cores, each associated with one of the cache memories;
- and
- a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some of the memory interfaces providing access paths to the main memory for multiple of the cache memories;
- with each of the memory interfaces being associated with a corresponding portion of the main memory, and including a directory controller for the portion of the main memory.
A method for managing cache memories associated with respective processor cores in a multicore processor that includes a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, the method comprising:
- providing access paths over at least some of the memory interfaces to the main memory for multiple of the cache memories;
- and
- associating each of the memory interfaces with a corresponding portion of the main memory, and operating a directory controller in each memory interface for the portion of the main memory.
A multicore processor comprising:
- a plurality of cache memories;
- a plurality of processor cores, each associated with one of the cache memories;
- one or more memory interfaces providing memory access paths from the cache memories to a main memory that is external to the multicore processor;
- and
- one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state, and wherein each directory controller and corresponding storage for directory state are included in the processor cores or the memory interfaces and are separate from the main memory.
Dependencies are inferred from the claim text.