Modular numerical control having low-jitter synchronization

A modular, numerical control unit having low-jitter synchronization, comprising:

• main computing means;
• and
• at least one controlling means, the at least one controlling means, starting from the main computing means, interconnected by serial data transmission means in the form of a series circuit, the at least one controlling means including:
• first receiving means for receiving a serial data stream arriving from a direction of the main computing means, an input to the first receiving means connected to a first channel of the serial data transmission means;
• first transmitting means for outputting a serial data stream, the first transmitting means connected to a second channel of the serial data transmission means;
• and
• clock recovery means for deriving a synchronous clock signal from the serial data stream arriving at the first receiving means and for supplying the synchronous clock signal to the first transmitting means, the synchronous clock signal used by the first transmitting means as a transmission clock signal, the serial data stream arriving at the first receiving means and the serial data stream output by the first transmitting means coupled to each other in phase-locked manner, the clock recovery means having an input connected to the first channel and an output connected to an input of the first transmitting means;
• wherein the at least one controlling means includes processing means to which the synchronous clock signal is supplied, the processing means for processing data included in the received serial data stream, at determined time intervals and for supplying the processed data to the first transmitting means;
• and
• wherein the at least one controlling means includes at least one control loop, the data included in the received serial data stream and processed by the processing means includes set point values for the at least one control loop.

A modular, numerical control unit having low-jitter synchronization, comprising:

• a main computer including a master clock-pulse generator;
• and
• a plurality of controller units, the controller units, starting from the main computer, interconnected by serial data transmission channels in the form of a series circuit, each controller unit including:
• a first receiver unit adapted to receive a serial data stream arriving from a direction of the main computer, an input to the first receiver unit connected to a first one of the serial data transmission channels;
• a first transmitter unit connected to a second one of the serial data transmission channels and adapted to output a serial data stream;
• and
• a clock recovery unit having an input connected to the first one of the serial data transmission channels and an output connected to an input of the first transmitter unit, the clock recovery unit adapted to derive a synchronous clock signal from the serial data stream arriving at the first receiver unit and to supply the synchronous clock signal to the first transmitter unit, the synchronous clock signal used by the first transmitter unit as a transmission clock signal, the serial data stream arriving at the first receiver unit and the serial data stream output by the first transmitter unit coupled to each other in phase-locked manner;
• wherein the synchronous clock signal derived by the clock recovery unit of each controller unit is coupled in phase-locked manner to a master clock signal generated by the master clock-pulse generator.