Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals

A method for performing data transactions, comprising:

• providing addressing signals over a shared address bus to a first memory device and a second memory device;
• providing a first clock signal and a second clock signal to the first memory device and the second memory device respectively, wherein the clock signals are derived from a common clock signal and the shared address bus is configured to provide the addressing signals to the first memory device on rising clock transitions of the first clock signal and provide the addressing signals to the second memory device on rising clock transitions of the second clock signal;
• and
• transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the first and second clock signals, wherein the separate narrow data buses are configurable as either a combined single wide data bus or as independent narrow data buses.

A DDR memory architecture comprising:

• a means for providing addressing signals over a shared address bus to a first memory device and a second memory device;
• a means for providing a first clock signal and a second clock signal to the first memory device and the second memory device respectively, wherein the clock signals are derived from a common clock signal and the shared address bus is configured to provide the addressing signals to the first memory device on rising clock transitions of the first clock signal and provide the addressing signals to the second memory device on rising clock transitions of the second clock signal;
• and
• a means for transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the first and second clock signals wherein the separate narrow data buses are configurable as either a combined single wide data bus or as independent narrow data buses.