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US 7,804,733 B2Granted
System and method for memory phase shedding
AssigneeIntel Corporation
InventorsJames W. Alexander, Edward R. Stanford, Devadatta V. Bodas, Howard David, Son H. Lam
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Abstract
Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described.
Claims13
A method for power management, comprising:
- activating all phases of a multi-phase memory voltage regulator;
- determining whether to decrease power supplied to at least one memory device, wherein determining whether to decrease the power supplied to the at least one memory device includes determining the extent to which a plurality of memory sockets are populated;
- if it is determined to decrease the power supplied to the at least one memory device, deactivating at least one phase of the multi-phase memory voltage regulator
- after the deactivating, setting a number of activated phases equal to a maximum number of phases;
- determining whether a central processing unit (CPU) associated with the multi-phase memory voltage regulator is in an active state or an idle state;
- if the CPU is in the idle state, deactivating at least one phase of the multi-phase memory voltage regulator;
- determining whether a power demand is less than a predetermined power threshold;
- and
- if the power demand is less than the predetermined threshold and the number of activated phases is greater than one, deactivating at least one phase of the multi-phase memory voltage regulator.
6 more elements
Dependencies are inferred from the claim text.