Memory control with selective retention
AssigneeST-Ericsson SA
InventorCornelis Hermanus Van Berkel
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AssigneeST-Ericsson SA
InventorCornelis Hermanus Van Berkel
Estimating the term…
The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.
A memory circuit having a plurality of memory cells for storing data, said memory circuit comprising:
A method of controlling data retention in a memory circuit, said method comprising the steps of:
An integrated memory circuit comprising:
Dependencies are inferred from the claim text.