Semiconductor memory device with signal aligning circuit

A signal aligning circuit, comprising:

• a plurality of pads receiving input signals in parallel 1 bit by 1 bit;
• a first transferring unit for transferring the input signals as first signals in synchronization with a first clock of an internal clock, and transferring the input signals as second signals in synchronization with a second clock of the internal clock;
• a second transferring unit for transferring the first signals in synchronization with the second clock of the internal clock;
• an aligning unit for outputting the first signals transferred from the second transferring unit and the second signals transferred from the first transferring unit to be synchronized in response to a synchronization signal delayed by a first delay value from the rising edge of the second clock of the internal clock;
• and
• an initialization signal generator for initializing the first and second transferring units after a delay of a second delay value greater than the first delay value from the rising edge of the second clock of the internal clock,
• wherein the initialization signal generator includes:
• a first D flip-flop for transferring a power supply voltage in synchronization with the rising edge of the first clock of the internal clock;
• a second D flip-flop for transferring an output of the first D flip-flop in synchronization with the rising edge of the second clock of the internal clock;
• a first delay unit for delaying an output of the second D flip-flop by a third delay value less than the first delay value;
• a second delay unit for delaying an output of the first delay unit by a fourth delay value having a delay time given by subtracting the third delay value from the second delay value;
• and
• an inverter for inverting a phase of the output of the second delay unit to output an initialization signal for initializing the shift register.