System and method for providing an EPROM with different gate oxide thicknesses

An electrically programmable read only memory (EPROM) device that comprises at least one memory cell, each memory cell comprising at most two transistors, including:

• a select transistor that comprises an n-channel metal oxide semiconductor (NMOS) transistor having a gate oxide layer that has thickness of approximately sixty Angstroms;
• and
• a breakdown transistor connected to the select transistor, wherein the breakdown transistor comprises a p-channel metal oxide semiconductor (PMOS) transistor having a gate oxide layer that has a thickness of approximately twenty Angstroms, wherein the gate oxide layer of the PMOS transistor is broken down when exposed to a programming current in a range of ten microamperes to one hundred microamperes,
• wherein the select transistor sources said programming current on to at least one of a drain, a source and an N well of the breakdown transistor, and
• a gate of the breakdown transistor is connected to a ground potential.

A method of operating an array of electrically programmable read only memory (EPROM) memory cells in which each memory cell comprises at most two transistors, the method comprising the steps of:

• for each memory cell, connecting to a wordline of the array a gate of an NMOS select transistor that has a gate oxide layer that has a thickness of approximately sixty Angstroms, connecting a drain of the NMOS select transistor to a bitline of the array, and connecting a source of the NMOS select transistor to a PMOS breakdown transistor that has a gate oxide layer that has a thickness of approximately twenty Angstroms;
• for each memory cell, connecting a gate of the PMOS breakdown transistor to ground, connecting a source, drain and N well of the PMOS breakdown transistor to the source of the NMOS select transistor, and
• wherein the NMOS select transistor sources a programming current on to the PMOS breakdown transistor;
• and
• programming a selected one of the memory cells of the array to a memory state by breaking down the gate oxide layer of the PMOS breakdown transistor of the selected memory cell, wherein the programming step comprises exposing the gate oxide layer of the PMOS breakdown transistor to said programming current in a range of ten microamperes to one hundred microamperes.