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US 7,804,708 B2Granted
Integrated circuit including an array of memory cells and method
AssigneeQimonda AG
InventorsUlrike Gruening-von Schwerin, Lothar Risch, Peter Baars, Klaus Muemmler, Stefan Tegen, Thomas Happ
Life of this patent
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Abstract
An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.
Claims6
An integrated circuit comprising:
- an array of memory cells, each cell comprising a resistively switching memory element coupled with its top side to a first selection line and coupled via a selection diode to a second selection line, the second selection line comprising a highly conductive component and arranged perpendicular to and below the first selection line;
- and
- wherein the selection diode is coupled to the bottom side of the memory element and to the bottom side of the second selection line.
Dependencies are inferred from the claim text.