US 7,804,706 B2Granted

Bottom electrode mask design for ultra-thin interlayer dielectric approach in MRAM device fabrication

AssigneeMagIC Technologies, Inc.

InventorsTom Zhong, Chyu-Jiuh Torng, Rongfu Xiao

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Abstract

A bottom electrode (BE) layout is disclosed that has four distinct sections repeated in a plurality of device blocks and is used to pattern a BE layer in a MRAM. A device section includes BE shapes and dummy BE shapes with essentially the same shape and size and covering a substantial portion of substrate. There is a via in a plurality of dummy BE shapes where each via will be aligned over a WL pad. A second bonding pad section comprises an opaque region having a plurality of vias. The remaining two sections relate to open field regions in the MRAM. The third section has a plurality of dummy BE shapes with a first area size. The fourth section has a plurality of dummy BE shapes with a second area size greater than the first area size to provide more complete BE coverage of an underlying etch stop ILD layer.

Claims20

Dependent claims

A BE layout (mask) for a memory device with an array of opaque features formed in a plurality of device blocks on a clear mask substrate, comprising:

(a) a device section which comprises a plurality of opaque BE shapes that are used to form active BE elements in the memory device, and a plurality of opaque dummy BE shapes that are used to form dummy BE elements in the memory device, said opaque BE shapes in adjacent device blocks have clear substrate regions formed therebetween that are substantially covered by said opaque dummy BE shapes and a certain number of opaque dummy BE shapes have openings formed therein that expose regions of clear substrate to allow alignment to WL pads in a device substrate;
(b) a bond pads section comprised of an opaque film with a plurality of openings formed therein, said openings expose regions of the clear substrate to allow alignment to bonding pad regions in a device substrate;
(c) a first open field section having an array of opaque dummy BE features with a first area size formed on the clear mask substrate;
and
(d) a second open field section having an array of opaque dummy BE features with a second area size that cover a substantial portion of the clear mask substrate wherein adjacent dummy BE features are separated by a space of clear mask substrate having a certain dimension, and said second area size is greater than said first area size.

2 more elements

A MRAM structure with a plurality of device blocks wherein each device block includes device regions and open field regions between adjacent device regions, comprising:

(a) a word line metal layer formed on a substructure, said word line metal layer includes a word line pad (WLP) and a word line (WL);
(b) a word line interlevel dielectric (ILD) layer formed coplanar with said WL and WLP and having a bonding pad region on a top surface thereof;
(c) an etch stop ILD layer formed on the WLP, WL, and word line ILD layer;
(d) a bottom electrode (BE) layer formed on and contacting the etch stop ILD layer, said BE layer includes a plurality of active BE elements in the device region with an active BE element above each WL, a plurality of first dummy BE elements in the device region with an opening formed in a first dummy BE above each WLP, a plurality of second dummy BE elements formed in the open field regions, and a BE dummy element with an opening formed therein above each bonding pad region;
(e) a MTJ layer with a hard mask formed thereon that includes a MTJ element contacting the active BE element above each WL;
(f) a MTJ ILD layer formed on the BE layer and coplanar with said hard mask on the MTJ layer;
and
(g) a bit line metal layer formed on the MTJ ILD and comprising a bit line (BIT) formed above the MTJ, a first bit line contact that connects with the WLP through the opening in the first dummy BE element, and a second bit line contact which connects to the bonding pad region through an opening in the dummy BE element above said bonding pad region.

5 more elements

A method of forming a MRAM structure with a plurality of device blocks wherein each device block includes device regions, and open field regions between adjacent device regions, comprising:

(a) providing a word line metal layer and a coplanar word line ILD layer formed on a substructure, said word line metal layer includes a word line pad (WLP) and a word line (WL);
(b) forming an etch stop ILD layer on the WLP, WL, and word line ILD layer;
(c) forming a bottom electrode (BE) layer on the etch stop ILD layer, said BE layer includes a plurality of active BE elements in the device regions with an active BE element above each WL, a plurality of first dummy BE elements in the device regions with an opening formed in a first dummy BE above each WLP, a plurality of second dummy BE elements formed in the open field regions, and a BE dummy element with an opening formed therein above each bonding pad region;
(d) forming a MTJ layer with a hard mask disposed thereon that includes a MTJ element contacting the active BE element above each WL;
(f) forming a MTJ ILD layer on the BE layer and coplanar with said hard mask on the MTJ layer;
and
(g) forming a bit line metal layer on the MTJ ILD and comprising a bit line (BIT) formed above each MTJ, a first bit line contact that connects with the WLP through the opening in the first dummy BE element, and a second bit line contact which connects to the bonding pad region through an opening in the dummy BE element above the bonding pad region.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/313,117Filed 17 Nov 2008
Published: US 2010/0123207 A120 May 2010
Granted: 28 Sep 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 61/00
Magnetic memory devices
G03F 1/36
Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles…
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
H10N 50/01
Galvanomagnetic devices: manufacture or treatment