Ferroelectric memory cell with access transmission gate

A memory device, comprising:

• a memory array that includes a number ferroelectric memory cells arranged in columns and rows;
• where a row of the ferroelectric memory cells is associated with a wordline, a complementary wordline, and a plateline;
• and where a column of the ferroelectric memory cells is associated with a bitline;
• where a ferroelectric memory cell at an intersection of the row and the column comprises:
• a ferroelectric capacitor having a first plate and a second plate, the first plate associated with a storage node of the ferroelectric memory cell and the second plate associated with the plateline;
• a complementary transmission gate configured to selectively couple the storage node to the bitline as a function of a wordline voltage and a complementary wordline voltage;
• and
• bias limiting circuitry configured to selectively alter voltage on the storage node.

A memory device, comprising:

• a memory array that includes a number ferroelectric memory cells arranged in columns and rows;
• where a row of the ferroelectric memory cells is associated with a wordline, a complementary wordline, and a plateline;
• and where a column of the ferroelectric memory cells is associated with a bitline;
• where a ferroelectric memory cell at an intersection of the row and the column comprises:
• a ferroelectric capacitor having a first plate and a second plate, the first plate associated with a storage node of the ferroelectric memory cell and the second plate associated with the plateline;
• a complementary transmission gate configured to selectively couple the storage node to the bitline as a function of a wordline voltage and a complementary wordline voltage;
• and
• bias limiting circuitry configured to selectively alter voltage on the storage node;
• where the ferroelectric memory cell further comprises:
• a p-type region comprising a p-type substrate or p-well;
• an n-type region formed within or laterally spaced from the p-type region;
• a first active region formed in the p-type region;
• a second active region formed in the n-type region and laterally separated from the first active region;
• a first gate region that runs over the first active region;
• and
• a second gate region that runs over the first and second active regions.

A memory device, comprising:

• a memory array that includes a number ferroelectric memory cells arranged in columns and rows;
• where a row of the ferroelectric memory cells is associated with a wordline, a complementary wordline, and a plateline;
• and where a column of the ferroelectric memory cells is associated with a bitline;
• where a ferroelectric memory cell at an intersection of the row and the column comprises:
• a ferroelectric capacitor having a first plate and a second plate, the first plate associated with a storage node of the ferroelectric memory cell and the second plate associated with the plateline;
• a complementary transmission gate configured to selectively couple the storage node to the bitline as a function of a wordline voltage and a complementary wordline voltage;
• and
• bias limiting circuitry configured to selectively alter voltage on the storage node;
• where the ferroelectric memory cell further comprises:
• a p-type region comprising a p-type substrate or p-well;
• an n-type region formed within or laterally spaced from the p-type region;
• a first active region formed in the p-type region;
• a second active region formed in the n-type region and laterally separated from the first active region;
• a first gate region that runs over the first and second active regions;
• and
• a second gate region that runs over the first and second active regions.