US 7,804,700 B2 · Semiconductor memory device with reduced coupling noise

Abstract

A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of bit lines and each of that includes a MIS transistor and a memory element, a decoder circuit for selecting a plurality of word lines, and a sense-amplifier circuit for determining information that is read from any of the plurality of memory cells to any of the plurality of bit lines, wherein a twist connector for switching the wiring order of the plurality of word lines is provided and level-stabilizing circuits, for supplying the potential level of a non-selected state to the plurality of word lines in the non-selected state are arranged in the area below the twist connector.

Claims13

Dependent claims

A semiconductor memory device comprising:

a plurality of word lines;
a plurality of bit lines;
a plurality of memory cells that are provided at intersections of said plurality of word lines and said plurality of bit lines, and each of said memory cells includes a MIS transistor and a memory element;
a decoder circuit for selecting said plurality of word lines;
and
a sense-amplifier circuit for determining information that is read from any of said plurality of memory cells to any of said plurality of bit lines;
wherein a twist connector is provided for switching wiring order of said plurality of word lines, and level-stabilizing circuits are arranged in an area below said twist connector, for supplying voltage level of a non-selected state to said plurality of word lines of a non-selected state.

4 more elements

A semiconductor memory device comprising:

a first area in which are arranged a plurality of first word lines each extending in parallel in a first direction and a plurality of memory cells connected to said plurality of first word lines;
a second area in which are arranged a plurality of second word lines each extending in parallel in said first direction and a plurality of memory cells connected to said plurality of second word lines;
and
a twist connection area arranged between said first area and said second area for realizing twist interconnection of said plurality of first word lines and said plurality of second word lines;
wherein said twist connection area includes:
a column-shaped first semiconductor layer;
a first gate layer formed on outer circumference of said first semiconductor layer with a first insulating film interposed;
a first wiring layer extending in a second direction that is orthogonal to said first direction;
a first contact for electrically connecting said first semiconductor layer and any of said plurality of first word lines;
a second contact for electrically connecting said first wiring layer and any of said plurality of second word lines;
and
a third contact for electrically connecting said first wiring layer and any of said plurality of second word lines.

9 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device with reduced coupling noise

Life of this patent

Semiconductor memory device with reduced coupling noise

Life of this patent

Abstract

Claims13