Hybrid ESD clamp

A method of manufacturing a circuit having a Gate Driven Power Transistor Device coupled to protect a line subject to transient overstress, the method comprising:

• forming the Gate Driven Power Transistor Device having a gate and one or more transistors;
• forming external circuitry coupled to the transistor device so as to provide an active clamp mode in which the gate of the transistor device is controlled to allow transient overstress current from the line through the transistor device, and the transistor device having a snapback mode in which the one or more transistors conduct the current if the transient overstress exceeds a predetermined threshold;
• and
• setting a threshold of the transistor device below a current capacity of a channel of the transistor device;
• wherein setting the threshold includes setting a distance between source regions of a transistor forming the transistor device to provide the desired threshold.