Managing yield for a parallel processing integrated circuit
AssigneeMassachusetts Institute of Technology
InventorAnant Agarwal
Life of this patent
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Abstract
A method for manufacturing an integrated circuit is described. The integrated circuit comprises a plurality of tiles, each tile comprising a processor and a switch coupled to neighboring tiles to form a network of tiles. The method includes identifying at least one tile that includes a fault, and forming data paths through one or more tiles to preserve communication in the network.
Claims19
A method for operating an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch coupled to neighboring tiles to form a network of tiles, the method comprising:
- identifying at least one tile that includes a fault;
- forming data paths through respective tiles;
- and
- compensating for an increased length in a path between tiles in the network caused by the forming of data paths through the respective tiles, including slowing a clock providing clock signals to the processors of at least two neighboring tiles through which the data paths are formed, to compensate for an increased propagation delay through parallel channels in each direction between the neighboring tiles.
An integrated circuit comprising:
- a plurality of tiles, each tile comprising
- a processor;
- and
- a switch including control circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and circuitry to form a data path through the tile to pass data between opposite sides of the tile without requiring operation of the control circuitry of the switch;
- and
- circuitry configured to compensate for an increased length in a path between tiles in a network caused by data paths formed through respective tiles, the circuitry comprising circuitry configured to slow a clock providing clock signals to the processors of at least two neighboring tiles through which the data paths are formed, to compensate for an increased propagation delay through parallel channels in each direction between the neighboring tiles.
An integrated circuit comprising:
- a plurality of tiles, each tile comprising
- a processor;
- and
- a switch including control circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, with the data paths between neighboring tiles including parallel channels in each direction, and the control circuitry including
- at least one multiplexer that select an input based on a control signal;
- at least one non-volatile memory coupled to the multiplexer and configured to control the control signal on the multiplexer to form a data path through the tile to pass data between opposite sides of the tile in response to the tile being in the same row or column as a faulty tile that includes at least one fault;
- clock distribution circuitry to provide clock signals from a clock to the processors of the tiles;
- and
- circuitry configured to compensate for an increased length in a path between tiles in a network caused by the data path formed through the faulty tile by slowing the clock to compensate for an increased propagation delay through the parallel channels in each direction.
Dependencies are inferred from the claim text.