Millimeter wave monolithic integrated circuits
AssigneeRaytheon Company
InventorsKenneth W. Brown, Andrew K. Brown
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AssigneeRaytheon Company
InventorsKenneth W. Brown, Andrew K. Brown
Estimating the term…
A millimeter wave amplifier constructed on a substrate and configured for use at a frequency of 75 GHz or higher, may include four amplifier stages. A first inter-stage filter, resonant at an operating frequency of the amplifier, may couple the output of the first stage to the input of the second stage. A second inter-stage filter, resonant at the operating frequency, may couple the output of the second stage to the input of the third stage. A third inter-stage filter, resonant at the operating frequency, may couple the output of the third stage to the input of the fourth stage. A plurality of bias supply leads that couple a gate bias voltage and a drain bias voltage to each of the amplifier stages. A plurality of bias line filters, resonant at the operating frequency, may be connected from at least some of the bias supply leads to a ground plane.
A millimeter wave amplifier constructed on a substrate, comprising:
A millimeter wave amplifier, constructed on a substrate, comprising:
A millimeter wave amplifier, constructed on a substrate, comprising:
A millimeter wave amplifier, constructed on a substrate, comprising:
A millimeter wave amplifier constructed on a substrate, comprising:
A millimeter wave amplifier constructed on a substrate, comprising:
Dependencies are inferred from the claim text.
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With semiconductor devices only: in integrated circuits
Indexing scheme relating to amplifiers: the supply or bias voltage or current at the drain side of a FET being continuously controlled by a…
Indexing scheme relating to amplifiers: two amplifying stages are coupled by means of a filter circuit
Indexing scheme relating to amplifiers: the bias of the gate of a FET being controlled by a control signal
About 2 years of term left · ends 6 Nov 2028 (estimated)
A portion of the disclosure of this patent document contains material which is subject to copyright protection. This patent document may show and/or describe matter which is or may become trade dress of the owner. The copyright and trade dress owner has no objection to the facsimile reproduction by anyone of the patent disclosure as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright and trade dress rights whatsoever.
1. Field
This disclosure relates generally to high frequency millimeter wave integrated circuit amplifiers, and more particularly to a multiple stage amplifier tuned to a specific operating frequency and having a serpentine signal path.
FIG. 1 shows a block diagram of an exemplary multiple stage amplifier.
FIG. 2 shows a schematic diagram of an exemplary multiple stage amplifier.
FIG. 3 depicts a physical layout of the exemplary amplifier of FIG. 2.
Description of Apparatus
The following description is based on an exemplary four-stage amplifier intended for operation at 95 GHz and configured to occupy a small die size relative to conventional amplifiers providing equivalent performance. The techniques and structure described herein may be scaled to amplifiers with more or fewer than four stages, and to frequencies less than or greater than 95 GHz.
Referring now to the block diagram of FIG. 1, the exemplary four-stage amplifier 100 may have first through fourth amplifier stages 110, 120, 130, 140 and first through third inter-stage coupling networks 115, 125, 135 formed on a semiconductor chip 102. An RF input signal to be amplified is introduced onto the semiconductor chip 102 at an RF input terminal 105. The RF input signal is amplified by the first amplifier stage 110 and then coupled to the input of the second amplifier stage 120 through the first inter-stage coupling network 115. The signal is then amplified by the second amplifier stage 120, coupled through the second inter-stage coupling network 125, amplifier by the third amplifier stage 130, coupled through the third inter-stage coupling network 135 and amplified by the fourth amplifier stage 140. The output from the fourth amplifier stage 140 exits the chip 102 at an RF Out pad 145. The four amplifier stages 110, 120, 130, 140 each receive a drain bias voltage Vd and a gate bias voltage Vg, which are introduced onto the die 102 at respective pads 160, 180.