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US 7,804,360 B2Granted
Dead-time locking circuit
AssigneeAdvanced Analog Technology, Inc.
InventorChien-Hao Chiu
Life of this patent
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Abstract
The dead-time locking circuit includes phase detector and a delay-comparator. The delay-comparator includes two input ends for receiving phase adjusting signal and the input-exchanging signal received by the class D amplifier. After comparing, the delay-comparator outputs a gate driving signal. The phase detector detects the phase difference between the output signal of the class D amplifier and the gate driving signal of the power transistor of the class D amplifier, and accordingly adjusts the rising/falling edges of the gate driving signal outputted from and the comparator via the charge-pump. In this way, the dead-time can be locked at the predetermined value.
Claims8
A dead-time locking circuit for controlling a class D amplifier, the dead-time locking circuit comprising:
- a first comparator, comprising:
- a positive input end for receiving a threshold voltage;
- a negative input end for receiving a gate driving signal;
- and
- an output end for outputting a first comparing signal;
- wherein the first comparing signal results from comparing the threshold voltage and the gate driving signal;
- a second comparator, comprising:
- a positive input end for receiving an output signal of the class D amplifier;
- a negative input end coupled to a first voltage source for receiving a first voltage;
- and
- an output end for outputting a second comparing signal;
- wherein the second comparing signal results from comparing the first voltage and the output signal of class D amplifier;
- a phase detector, comprising:
- a first input end coupled to output end of the first comparator for receiving the first comparing signal;
- a second input end coupled to the output end of the second comparator for receiving the second comparing signal;
- a first output end for outputting a phase-leading signal;
- and
- a second input end for outputting a phase-lagging signal;
- wherein when phase of the first comparing signal leads the phase of second comparing signal, the phase detector outputs the phase-leading signal;
- when the phase of the first comparing signal lags the phase of the second comparing signal, the phase detector outputs the phase-lagging signal;
- a first and a second current sources for providing a first current;
- a first transistor, comprising:
- a first end coupled to the first current source;
- a second end, and
- a control end coupled to the first output end of the phase detector;
- wherein when the first transistor receives the phase-leading signal, the first current is outputted at the second end of the first transistor;
- a second transistor, comprising:
- a first end coupled to the second current source;
- a second end coupled to the second end of the first transistor;
- and
- a control end coupled to the second output end of the phase detector;
- wherein when the second transistor receives the phase-lagging signal, the first current is drained at the second end of the second transistor;
- a first capacitor coupled between the second end of the first transistor, the second end of the second transistor, and a second voltage source;
- a third current source for providing a second current;
- a second capacitor coupled between the third current source and the second voltage source;
- a third transistor, comprising:
- a first end coupled to the second voltage source;
- a second end coupled to the third current source and the second capacitor;
- and
- a control end for receiving a switching control signal;
- wherein when the switching control signal turns the third transistor on, the second current source discharges the second capacitor through the third transistor;
- when the switching control signal turns the third transistor off, the third current source charges the second capacitor;
- and
- a third comparator, comprising:
- a positive input end coupled to the second capacitor;
- a negative input end coupled to the first capacitor;
- an output end for outputting a switch control signal;
- wherein the switch control signal results from comparing voltages of the first capacitor and the second capacitor.
45 more elements
A dead-time locking circuit for controlling a class D amplifier, the dead-time locking circuit comprising:
- a falling dead-time locking circuit, comprising:
- a first comparator, comprising:
- a positive input end for receiving a first turning-on threshold voltage;
- a negative input end for receiving a first gate driving signal;
- and
- an output end for outputting a first comparing signal;
- wherein the first comparing signal results from comparing the first turning-on threshold voltage and the first gate driving signal;
- a second comparator, comprising:
- a positive input end for receiving an output signal of the class D amplifier;
- a negative input end coupled to a first voltage source for receiving a first voltage;
- and
- an output end for outputting a second comparing signal;
- wherein the second comparing signal results from comparing the first voltage and the output signal of the class D amplifier;
- a phase detector, comprising:
- a first input end coupled to output end of the first comparator for receiving the first comparing signal;
- a second input end coupled to the output end of the second comparator for receiving the second comparing signal;
- a first output end for outputting a phase-leading signal;
- and
- a second input end for outputting a phase-lagging signal;
- wherein when phase of the first comparing signal leads the phase of second comparing signal, the phase detector outputs the phase-leading signal;
- when the phase of the first comparing signal lags the phase of the second comparing signal, the phase detector outputs the phase-lagging signal;
- a first and a second current sources for providing a first current;
- a first transistor, comprising:
- a first end coupled to the first current source;
- a second end;
- and
- a control end coupled to the first output end of the phase detector;
- wherein when the first transistor receives the phase-leading signal, the first current is outputted at the second end of the first transistor;
- a second transistor, comprising:
- a first end coupled to the second current source;
- a second end coupled to the second end of the first transistor;
- and
- a control end coupled to the second output end of the phase detector;
- wherein when the second transistor receives the phase-lagging signal, the first current is drained at the second end of the second transistor;
- a first capacitor coupled between the second end of the first transistor, the second end of the second transistor, and a second voltage source;
- a third current source for providing a second current;
- a second capacitor coupled between the third current source and the second voltage source;
- a third transistor, comprising:
- a first end coupled to the second voltage source;
- a second end coupled to the third current source and the second capacitor;
- and
- a control end for receiving an inverted signal of a switch control signal;
- wherein when the inverted signal of the switching control signal turns the third transistor on, the second current source discharges the second capacitor through the third transistor;
- when the inverted signal of the switching control signal turns the third transistor off, the third current source charges the second capacitor;
- and
- a third comparator, comprising:
- a positive input end coupled to the second capacitor;
- a negative input end coupled to the first capacitor;
- an output end for outputting a result of comparing voltages respectively on the first capacitor and the second capacitor;
- and
- an inverter coupled to the output end of the third comparator for inverting a received signal as a first switch control signal;
- and
- a rising dead-time locking circuit, comprising:
- a first comparator, comprising:
- a negative input end for receiving a second turning-on threshold voltage;
- a positive input end for receiving a second gate driving signal;
- and
- an output end for outputting a first comparing signal;
- wherein the first comparing signal results from comparing the second turning-on threshold voltage and the second gate driving signal;
- a second comparator, comprising:
- a negative input end for receiving the output signal of the class D amplifier;
- a positive input end coupled to the second voltage source for receiving a second voltage;
- and
- an output end for outputting a second comparing signal;
- wherein the second comparing signal results from comparing the second voltage and the output signal of the class D amplifier;
- a phase detector, comprising:
- a first input end coupled to output end of the first comparator for receiving the first comparing signal;
- a second input end coupled to the output end of the second comparator for receiving the second comparing signal;
- a first output end for outputting a phase-leading signal;
- and
- a second input end for outputting a phase-lagging signal;
- wherein when phase of the first comparing signal leads the phase of second comparing signal, the phase detector outputs the phase-leading signal;
- when the phase of the first comparing signal lags the phase of the second comparing signal, the phase detector outputs the phase-lagging signal;
- a first and a second current sources for providing a first current;
- a first transistor, comprising:
- a first end coupled to the first current source;
- a second end;
- and
- a control end coupled to the first output end of the phase detector;
- wherein when the first transistor receives the phase-leading signal, the first current is outputted at the second end of the first transistor;
- a second transistor, comprising:
- a first end coupled to the second current source;
- a second end coupled to the second end of the first transistor;
- and
- a control end coupled to the second output end of the phase detector;
- wherein when the second transistor receives the phase-lagging signal, the first current is drained at the second end of the second transistor;
- a first capacitor coupled between the second end of the first transistor, the second end of the second transistor, and the second voltage source;
- a third current source for providing the second current;
- a second capacitor coupled between the third current source and the second voltage source;
- a third transistor, comprising:
- a first end coupled to the second voltage source;
- a second end coupled to the third current source and the second capacitor;
- and
- a control end for receiving a switching control signal;
- wherein when the switching control signal turns the third transistor on, the second current source discharges the second capacitor through the third transistor;
- when the switching control signal turns the third transistor off, the third current source charges the second capacitor;
- and
- a third comparator, comprising:
- a positive input end coupled to the second capacitor;
- a negative input end coupled to the first capacitor;
- and
- an output end for outputting a result of comparing voltages respectively on the first capacitor and the second capacitor as a second switch control signal.
99 more elements
Dependencies are inferred from the claim text.