Level-restored for supply-regulated PLL

A synchronous system, comprising:

• a clock source that is configured to generate an input clock signal having an input frequency;
• a level-restored clock generator, coupled to the input clock source, comprising:
• a forward path portion that receives the clock signal at a first input and outputs a first signal having a variable amplitude and a first frequency, the first signal being based on the input clock signal;
• a level restorer, coupled to an output of the forward path portion, that is configured to convert the first signal to a second signal having a level-restored amplitude that can be a value that is either greater or less than the variable amplitude of the first signal;
• and
• a feedback path, coupled between the level restorer and a second input of the forward path portion, that is configured to return the second signal to the forward path portion;
• a clock distribution unit, coupled to the level-restored clock generator, that is configured to generate a distributed clock signal based on the second signal;
• and
• a plurality of processors, coupled to the clock distribution unit, that are configured to perform digital operations in synchrony with the distributed clock signal.

A phase locked loop device, comprising:

• a forward path portion that receives an input clock signal at an input, the forward path portion outputting a first signal having a variable amplitude and a first frequency;
• a level restorer, coupled to an output of the forward path portion, that is configured to convert the first signal to a second signal having a level-restored amplitude with a value that can be either greater or less than the variable amplitude of the first signal;
• and
• a feedback path, coupled between the level restorer and the input of the forward path portion.

A method of synthesizing a digital clock signal, comprising:

• receiving an input clock signal at an input of a forward path portion of a phase locked loop;
• generating a first differential signal having a variable amplitude and a first frequency from the input clock signal;
• and
• converting the first differential signal to a second differential signal having a level-restored amplitude that can be either greater or less than the variable amplitude.

A processor, comprising:

• a clock source that is configured to generate an input clock signal having an input frequency;
• a forward path portion that is configured to receive the input clock signal at a first input and generate a first signal having a variable amplitude and a first frequency, the forward path portion including a supply-regulated voltage controlled oscillator, the first signal being based on the input clock signal;
• and
• a level restorer, coupled to an output of the forward path portion, that is configured to convert the first signal to a second signal having the first frequency and a level-restored amplitude that can be a value that is either greater or less than the variable amplitude of the first signal, wherein the variable amplitude of the first signal and the level-restored amplitude of the second signal correspond to a level-restorer input voltage and a level-restorer output voltage, respectively.