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US 7,804,337 B2Granted
Method and apparatus of SFDR enhancement
AssigneeTexas Instruments Incorporated
InventorsRobert F. Payne, Marco Corsi
Life of this patent
Estimating the term…
Abstract
A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and conventional S/H circuits is the use of a peaking circuit. This peaking circuit generally provides increased current to switching transistor when transitioning between track and hold which can increase the Spurious-Free Dynamic Range (SFDR) as low frequencies, by as much as 15dB.
Claims18
A track-and-hold circuit that is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal, the track-and-hold circuit comprising:
- a bi-directional current source that sources and sinks current through a first output node and a second output node, wherein the bi-directional current source includes:
- a hold terminal that is adapted to provide the hold signal;
- a track terminal that is adapted to provide the track signal;
- a first differential input circuit having a plurality of transistors, wherein the first differential input circuit is adapted to receive the track signal and the hold signal and is coupled to the first and second output nodes;
- a second differential input circuit having a plurality of transistors, wherein the differential input circuit is adapted to receive the track signal and the hold signal and is coupled to the first and second output nodes;
- and
- a peaking circuit that is coupled to the first and second differential input circuits, wherein the peaking circuit causes the current through at least one of the transistors to exceed a threshold for a predetermined period when the track-and-hold circuit transitions from track to hold;
- a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal;
- a resistor coupled to an output of the unity gain amplifier;
- and
- a capacitor coupled between the resistor and ground.
8 more elements
A track-and-hold circuit that is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal, the track-and-hold circuit comprising:
- a bi-directional current source that sources and sinks current through a first output node and a second output node, wherein the bi-directional current source includes:
- a hold terminal that is adapted to provide the hold signal;
- a track terminal that is adapted to provide the track signal;
- a first bipolar junction transistor (BJT) that is coupled to the hold terminal at its base;
- a second BJT that is coupled to the hold terminal at its base;
- a third BJT that is coupled to the track terminal at its base;
- a fourth BJT that is coupled to the track terminal at its base;
- a fifth BJT that is coupled to the collector of the first BJT at its base;
- a sixth BJT that is coupled to the collector of the third BJT at its base and that is coupled to the emitter of the fifth BJT at its emitter;
- a seventh BJT that is coupled to the collector of the second BJT at its base;
- an eighth BJT that is coupled to the collector of the fourth BJT at its base and that is coupled to the emitter of the seventh BJT at its emitter;
- and
- a peaking circuit that is coupled to the bases of the fifth, sixth, seventh and eighth BJTs, wherein the peaking circuit causes the current through at least one of the transistors to exceed a threshold for a predetermined period when the track-and-hold circuit transitions from track to hold;
- a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal;
- a resistor coupled to an output of the unity gain amplifier;
- and
- a capacitor coupled between the resistor and ground.
14 more elements
An apparatus comprising:
- an analog-to-digital converter (ADC) pipeline having a plurality of stages, wherein the ADC pipeline receives an analog input signal and outputs a digital signal across a plurality of channels, and wherein at least one stage includes a track-and-hold amplifier having a switched current source that includes:
- a bi-directional current source that sources and sinks current through a first output node and a second output node, wherein the bi-directional current source includes:
- a hold terminal that is adapted to provide the hold signal;
- a track terminal that is adapted to provide the track signal;
- a first bipolar junction transistor (BJT) that is coupled to the hold terminal at its base;
- a second BJT that is coupled to the hold terminal at its base;
- a third BJT that is coupled to the track terminal at its base;
- a fourth BJT that is coupled to the track terminal at its base;
- a fifth BJT that is coupled to the collector of the first BJT at its base;
- a sixth BJT that is coupled to the collector of the third BJT at its base and that is coupled to the emitter of the fifth BJT at its emitter;
- a seventh BJT that is coupled to the collector of the second BJT at its base;
- an eighth BJT that is coupled to the collector of the fourth BJT at its base and that is coupled to the emitter of the seventh BJT at its emitter;
- and
- a peaking circuit that is coupled to the bases of the fifth, sixth, seventh and eighth BJTs, wherein the peaking circuit causes the current through at least one of the transistors to exceed a threshold for a predetermined period when the track-and-hold circuit transitions from track to hold;
- a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal;
- a resistor coupled to an output of the unity gain amplifier;
- and
- a capacitor coupled between the resistor and ground;
- and
- an ADC driver that is coupled to the ADC pipeline.
17 more elements
Dependencies are inferred from the claim text.