Back to results
US 7,804,332 B2Granted
Circuit configurations having four terminal JFET devices
AssigneeSuVolta, Inc.
InventorAshok Kumar Kapoor
Life of this patent
Estimating the term…
Abstract
Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.
Claims20
A logic circuit, comprising:
- at least one input node;
- at least one output node;
- and
- a plurality of junction field effect transistors (JFETs) coupled between the at least one input node and output node, each JFET including a first gate and a second gate of a first conductivity type and a channel region of a second conductivity type between the first gate and second gate, the channel region connecting a source region to a drain region both of the second conductivity type, the second gate being separately controllable with respect to the first gate.
1 more element
A circuit, comprising:
- a plurality of junction field effect transistors (JFETs) each having a front gate and a back gate, including at least one first conductivity type JFET having a source-drain path coupled between a first power supply node and an internal node, and at least one second conductivity type JFET having a source-drain path coupled between a second power supply node and the internal node;
- wherein
- that at least one first conductivity type JFET has a front gate coupled to a first input node and a back gate coupled to a second input node, and the at least one second conductivity type JFET has a front gate coupled to the first input node.
A storage circuit, comprising:
- a first JFET of a first channel conductivity type having a source coupled to a first supply node, a drain coupled to a first latch node, a first gate coupled to a first input node, and a second gate coupled to a second latch node;
- and
- a second JFET of the first channel conductivity type having a source coupled to the first supply node, a drain coupled to the second latch node, a first gate coupled to a second input node, and a second gate coupled to the first latch node.
Dependencies are inferred from the claim text.