Adaptive keeper circuit to control domino logic dynamic circuits using rate sensing technique

A method of operating an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay by maintaining a node Y at a voltage VDD during evaluation phase as demanded by the input logic, said method comprising steps of:

• i. generating reference rate by appropriately biasing reference rate transistor M4 using VBIAS;
• ii. charging the node Y to VDD through transistor M7 to cause feedback transistor M2 to shut OFF and node VSEN to VDD through transistor M3 causing transistors M6 and M1 to shut OFF during pre-charge phase when clock signal is low;
• iii. discharging the charged node VSEN at rate higher than the charged node Y causing the keeper transistor M1 to pump a larger current into node Y compared to leakage current of pull down NMOS logic which causes M2 to turn ON slowly;
• iv. replenishing all the leaked charge to the node Y using the pumped current which in-turn causes the transistor M2 to slowly shut off;
• and
• v. accelerating the discharge of node VSEN to turn ON the keeper transistor M1 faster, causing the transistor M1 to turn on pulling the node Y back to VDD and thereby shutting the feedback transistor M2 off.

A method of operating an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at a given noise robustness with less overhead in area, power and delay by maintaining a node Y at GND during evaluation phase as demanded by the input logic, said method comprising steps of:

• i. generating reference rate by appropriately biasing reference rate transistor M4 using VBIAS;
• ii. charging the node Y to VDD through transistor M7 to cause feedback transistor M2 to shut OFF and node VSEN to VDD through transistor M3 causing transistors M6 and M1 to shut OFF during pre-charge phase when clock signal is low;
• and
• iii. turning ON one of pull down legs to discharge the charge at node Y at a higher rate compared to discharge at the node VSEN causing feedback shutoff transistor M5 to turn off thereby slowing down the discharge at the node VSEN further turning on the feedback transistor M2 much faster compared to the keeper transistor M1 and thereby pulling the node VSEN to VDD by drawing large current through M2 causing M1 to shut off to maintain the node Y at GND.