Source/emitter follower buffer driving a switching load and having improved linearity

A buffer comprising:

• a input terminal;
• an output terminal;
• a follower transistor that is coupled to the input terminal;
• a first bias transistor that is coupled to the follower transistor and the output terminal and that receives a first bias voltage;
• a second bias transistor that is coupled between the first bias transistor and ground and that receives a second bias voltage;
• and
• a capacitor that is coupled between the input terminal and a node between the first bias transistor and the second bias transistor.

An analog-to-digital converter comprising:

• a buffer having:
• an input terminal that receives an input signal;
• an output terminal;
• a first NPN transistor that is coupled to the input terminal at its base, that receives a supply voltage at its collector, and that is coupled to the output terminal at its emitter;
• a second NPN transistor that is coupled to output terminal at its collector and that receives a first bias voltage at its base;
• an NMOS transistor that is coupled to the emitter of the second NPN transistor at its drain, that receives a second bias voltage at its gate, and that is coupled to ground at its source;
• and
• a capacitor that is coupled between the input terminal and the drain of the NMOS transistor;
• and
• analog-to-digital conversion circuitry that is coupled to the output terminal of the buffer.