Dynamically adjusting operation of a circuit within a semiconductor device

An apparatus, comprising:

• a first reference circuit configured to provide a particular impedance and comprising a first plurality of switching devices and a first resistive device coupled to each other in parallel, wherein the first plurality of switching devices have a first doping polarity;
• a second reference circuit configured to provide the particular impedance and comprising a second plurality of switching devices and a second resistive device coupled to each other in parallel, wherein the second plurality of switching devices have a second doping polarity opposite the first doping polarity;
• a third plurality of switching devices coupled to each other in parallel, wherein the third plurality of switching devices are coupled in series with the first reference circuit between a supply node and a supply return node and wherein the third plurality of switching devices have the second doping polarity;
• a fourth plurality of switching devices coupled to each other in parallel, wherein the fourth plurality of switching devices are coupled in series with the second reference circuit between the supply node and the supply return node and wherein the fourth plurality of switching devices have the first doping polarity;
• first processing logic coupled to the third plurality of switching devices and configured to selectively enable and disable a combination of switching devices of the third plurality of switching devices that results in an impedance of the enabled switching devices more closely matching the particular impedance than at least one other combination of enabled and disabled switching devices of the third plurality of switching devices;
• and
• second processing logic coupled to the fourth plurality of switching devices and configured to selectively enable and disable a combination of switching devices of the fourth plurality of switching devices that results in an impedance of the enabled switching devices more closely matching the particular impedance than at least one other combination of enabled and disabled switching devices of the fourth plurality of switching devices.

An integrated circuit for driving an output signal, comprising:

• a first reference circuit configured to provide a particular impedance and comprising a first plurality of switching devices and a resistive device coupled to each other in parallel, wherein the first plurality of switching devices have a first doping polarity;
• a second plurality of switching devices coupled to each other in parallel, wherein the second plurality of switching devices are coupled in series with the first reference circuit between a supply node and a supply return node, and wherein the second plurality of switching devices have a second doping polarity opposite the first doping polarity;
• and
• a first processing logic coupled to the second plurality of switching devices and configured to selectively enable and disable a combination of switching devices of the second plurality of switching devices that results in an impedance of the enabled switching devices more closely matching the particular impedance than at least one other combination of enabled and disabled switching devices of the second plurality of switching devices, wherein the first processing logic is further configured to generate a first plurality of match control signals representative of the selected combination of enabled and disabled switching devices of the second plurality of switching devices;
• and
• a first driver circuit, comprising:
• a first plurality of primary driver devices;
• and
• a first plurality of auxiliary driver branches coupled in parallel to the first plurality of primary driver devices, each of the first plurality of auxiliary driver branches comprising a first plurality of auxiliary driver devices that are responsive to a same input signal as the first plurality of primary driver devices;
• and
• a second processing logic coupled to the first plurality of auxiliary driver branches and configured to selectively enable and disable a combination of the auxiliary driver branches of the first plurality of auxiliary driver branches in response to the first plurality of match control signals to drive a common first output signal in parallel with the first plurality of primary driver devices.