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US 7,804,321 B2Granted
Circuits and methods for testing FPGA routing switches
AssigneeActel Corporation
InventorsJonathan W. Greene, John McCollum, Volker Hecht
Life of this patent
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Abstract
An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
Claims9
An FPGA architecture including:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of wiring tracks;
- multiplexers having non-volatile switches having control gates, the control gates of different switches coupled to ones of the word lines;
- buffers connecting the switches to the wiring tracks, the buffers having a ground connection coupled to a signal NGND;
- and
- at least some of the switches being a tie-off switch coupleable to a tie-off potential, each tie-off switch coupleable to one of the of bit lines.
4 more elements
A field-programmable gate array architecture including:
- a plurality of word lines;
- a plurality of wiring tracks;
- a plurality of multiplexers, each multiplexer having switches arranged in rows, each row associated with one of the word lines, each row of switches able to be forced on or off in response to signals driven onto the one of the word lines associated with the row;
- the switches in each multiplexer coupled to at least one of the wiring tracks through a buffer, all of the buffers having outputs that can be forced to a known state by a common signal;
- and
- at least some of the switches being tie-off switches coupleable to one of at least one tie-off potential, and a node that can be observed for testing.
3 more elements
Dependencies are inferred from the claim text.