US 7,804,176 B2Granted

Semiconductor device

AssigneeRenesas Electronics Corporation

InventorsKazuko Hanawa, Takashi Kikuchi, Koichi Kanemoto, Michiaki Sugiyama, Chikako Imura

Life of this patent

Estimating the term…

Loading patent…

Abstract

This invention is to provide a nonvolatile memory device that enhances a size reduction and mass productivity while ensuring reliability and signal transmission performance. A nonvolatile memory chip having a first side formed with no pads and a second side formed with pads is mounted on a mounting substrate. A control chip for controlling the nonvolatile memory chip is mounted on the nonvolatile memory chip. The control chip has a first pad row corresponding to the pads of the nonvolatile memory chip. The first pad row is mounted adjacent to the first side of the nonvolatile memory chip. The first pad row of the control chip and a first electrode row formed on the mounting substrate are connected via a first wire group. The pads of the nonvolatile memory chip and a second electrode row formed on the mounting substrate are connected via a second wire group. The first electrode row and the second electrode row are connected through wirings formed in the mounting substrate.

Claims8

Dependent claims

A semiconductor device comprising:

(a) a substrate having a front surface, a plurality of electrodes formed on the front surface, and a rear surface opposed to the front surface,
wherein the plurality of electrodes include a plurality of first electrodes and a plurality of second electrodes;
(b) a memory chip having a first main surface, a plurality of first bonding pads formed on the first main surface, and a first back surface opposed to the first main surface,
wherein the first main surface has a pair of first sides mutually opposed and a pair of second sides mutually opposed and intersecting with the first sides,
wherein the plurality of first bonding pads are arranged along one of the first sides, and not arranged along either of the second sides, and
wherein the memory chip is mounted over the front surface of the substrate such that the first back surface of the memory chip opposes the front surface of the substrate;
(c) a control chip having a second main surface, a plurality of second bonding pads formed on the second main surface, and a second back surface opposed to the second main surface,
wherein the second main surface has a pair of third sides mutually opposed and a pair of fourth sides mutually opposed and intersecting with the third sides,
wherein the plurality of second bonding pads are arranged along one of the fourth sides, and not arranged along either of the third sides and the other of the fourth sides,
wherein a size of the control chip is smaller than that of the memory chip in a plan view,
wherein the control chip is mounted over the first main surface of the memory chip such that the one of the fourth sides of the control chip is arranged next to one of the second sides of the memory chip, and
wherein the control chip is mounted over the first main surface of the memory chip such that a distance between the one of the fourth sides of the control chip and the one of the second sides of the memory chip is smaller than a distance between the other of the fourth sides of the control chip and the other of the second sides of the memory chip;
(d) a plurality of first wires coupling the plurality of first bonding pads with the plurality of first electrodes;
(e) a plurality of second wires coupling the plurality of second bonding pads with the plurality of second electrodes;
(f) a sealing body sealing the memory chip, the control chip, a plurality of first wires and a plurality of second wires;
and
(g) a plurality of external terminals formed on the rear surface of the substrate,
wherein the plurality of first electrodes are arranged along the one of the first sides;
and
wherein the plurality of second electrodes are arranged along one of the second sides of the memory chip.

17 more elements

A semiconductor device comprising:

(a) a substrate having a front surface, a plurality of electrodes formed on the front surface, and a rear surface opposed to the front surface,
wherein the plurality of electrodes include a plurality of first electrodes and a plurality of second electrodes;
(b) a memory chip having a first main surface, a plurality of first bonding pads formed on the first main surface, a first back surface opposed to the first main surface,
wherein the first main surface has a pair of first sides and a pair of second sides intersecting with the first sides,
wherein the plurality of first bonding pads are arranged along one of the first sides, and not arranged along either of the second sides and the other of the first sides, and
wherein the memory chip is mounted over the front surface of the substrate such that the first back surface of the memory chip opposes the front surface of the substrate;
(c) a control chip having a second main surface, a plurality of second bonding pads formed on the second main surface, a second back surface opposed to the second main surface,
wherein the second main surface has a pair of third sides and a pair of fourth sides intersecting with the third sides,
wherein the plurality of second bonding pads are arranged along one of the fourth sides, and are not arranged along either of the third sides and the other of the fourth sides
wherein a size in a plain view of the control chip is smaller than that of the memory chip,
wherein the control chip is mounted over the first main surface of the memory chip such that the one of the fourth sides is arranged next to the other of the first sides, or one of the pair of second sides of the memory chip, and
wherein the control chip is mounted over the first main surface of the memory chip such that a distance between the one of the fourth sides of the control chip and the side of the memory chip arranged next to the one of the fourth sides of the control chip is smaller than a distance between the other of the fourth sides of the control chip and the side of the memory chip arranged next to the other of the fourth sides of the control chip;
(d) a plurality of first wires coupling the plurality of first bonding pads with the plurality of first electrodes;
(e) a plurality of second wires coupling the plurality of second bonding pads with the plurality of second electrodes;
(f) a sealing body sealing the memory chip, the control chip, a plurality of first wires and a plurality of second wires;
(g) a plurality of external terminals formed on the rear surface of the substrate,
wherein the plurality of first electrodes are arranged along the one of the first sides;
and
wherein the plurality of second electrodes are arranged along the side of the memory chip arranged next to the one of the fourth sides of the control chip.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/626,286Filed 23 Jan 2007
Priority: JP 2006-04546322 Feb 2006
Published: US 2007/0194454 A123 Aug 2007
Granted: 28 Sep 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10W 90/00
Package configurations
G11C 5/06
Details of stores covered by group G11C11/00: arrangements for interconnecting storage elements electrically, e.g. by wiring
H10W 72/5449
Dispositions of bond wires: not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
H10W 72/5522
Comprising metals or metalloids, e.g. silver: comprising gold [Au]