Recessed shallow trench isolation
AssigneeMacronix International Co., Ltd.
InventorsChih Chieh Yeh, Wen Jer Tsai
Life of this patent
Estimating the term…
Abstract
In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations. In some embodiments, recessed shallow trench isolation structures are formed.
Claims27
A semiconductor manufacturing method, comprising:
- forming shallow trench isolation structures on at least regions of a wafer allotted to memory devices, including:
- forming trenches of the shallow trench isolation structures;
- depositing isolation dielectric into the trenches and onto intermediate regions between the trenches;
- removing the isolation dielectric until at least the isolation dielectric covering the intermediate regions is removed from at least the regions of the wafer allotted to memory devices;
- and
- after said removing the isolation dielectric covering the intermediate regions, at least partly removing the isolation dielectric from the trenches in at least the regions of the wafer allotted to memory devices;
- and
- forming control circuitry coupled to the memory devices, the control circuitry measuring a current component flowing between a substrate region and a current terminal in the memory devices to read data in the memory devices.
A method of manufacturing a memory integrated circuit, comprising:
- forming memory circuitry including memory circuitry trenches, including:
- forming first shallow trench isolation structures including first isolation dielectric, the first isolation dielectric filling the memory circuitry trenches incompletely, the memory circuitry trenches characterized a first trench depth between top edge to bottom;
- and
- forming control circuitry coupled to the memory circuitry, the control circuitry including control circuitry trenches, including:
- forming second shallow trench isolation structures including second isolation dielectric, the second isolation dielectric filling the control circuitry trenches more completely than the first isolation dielectric fills the memory circuitry trenches, the control circuitry trenches characterized a second trench depth between top edge to bottom, the second trench depth having a magnitude larger than the first trench depth.
A method of manufacturing a memory integrated circuit, comprising:
- forming memory circuitry including memory circuitry trenches, including:
- forming shallow trench isolation structures oriented along a direction of a substrate, the shallow trench isolation structures including first isolation dielectric, the first isolation dielectric filling the memory circuitry trenches incompletely, the memory circuitry trenches characterized a first trench depth between top edge to bottom;
- forming intermediate regions between the memory circuitry trenches, the intermediate regions oriented along the direction of the substrate, including:
- forming nonvolatile memory structures forming nonvolatile memory devices, including:
- forming a charge storage structure;
- and
- forming one or more dielectric structures at least partly between the charge storage structure and the substrate region and at least partly between the charge storage structure and a source of gate voltage,
- wherein the memory circuitry supports a channel between neighboring nonvolatile memory devices sharing a common one of said intermediate regions, the channel supporting a first current component having a first orientation defined by a trench of at least one shallow trench isolation structure adjacent to the common intermediate region, and a second current component having a second orientation defined by a surface of the common intermediate region;
- and
- forming control circuitry coupled to the memory circuitry, including:
- forming second shallow trench isolation structures including second isolation dielectric, the second isolation dielectric at least partly filling the control circuitry trenches, the control circuitry trenches characterized a second trench depth between top edge to bottom, the second trench depth having a magnitude larger than the first trench depth.
Dependencies are inferred from the claim text.