Integrated circuit structure, design structure, and method having improved isolation and harmonics

#This application is related to the following co-pending application filed concurrently herewith by the same Applicants and assigned to the same Assignee, namely, International Business Machines Corporation (IBM Corporation): “INTEGRATED CIRCUIT STRUCTURE, DESIGN STRUCTURE, AND METHOD HAVING IMPROVED ISOLATION AND HARMONICS”. The complete disclosure of this related co-pending application is incorporated herein by reference.

#The embodiments of the invention generally relate to integrated circuit structures and, more specifically, to an integrated circuit structure, a design structure for the integrated circuit structure and a method of forming the integrated circuit structure with improved isolation and, in the case of a radio frequency (RF) device (e.g., a RF switch) with reduced harmonics.

#Integrated circuit devices formed in or above the active semiconductor layer (e.g., the active silicon layer) of a semiconductor-on-insulator (SOI) wafer often suffer from performance degradation due to coupling capacitance between the integrated circuit devices and the wafer substrate (e.g., a silicon substrate). Some integrated circuit devices, such as radio frequency (RF) switches, further suffer due to harmonics resulting from the resulting charge layer at the interface between the SOI insulator layer (e.g., the buried oxide (BOX) layer) and the wafer substrate. Therefore, there is a need in the art for a semiconductor structure that is formed using an SOI wafer and that has reduced harmonics and improved isolation between the active semiconductor layer and the wafer substrate.

#The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawing to scale and in which:

#FIG. 1 is a cross-section diagram illustrating an embodiment of the semiconductor structure of the present invention;

#FIG. 2 is a cross-section diagram illustrating an alternative configuration for the embodiment of the semiconductor structure of FIG. 1;

#The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description.

#As mentioned above, integrated circuit devices formed in or above the active semiconductor layer (e.g., the active silicon layer) of a semiconductor-on-insulator (SOI) wafer often suffer from performance degradation due to coupling capacitance between the integrated circuit devices and the wafer substrate (e.g., a silicon substrate). Some integrated circuit devices, such as radio frequency (RF) switches, further suffer due to harmonics resulting from the resulting charge layer at the interface between the SOI insulator layer (e.g., the buried oxide (BOX) layer) and the wafer substrate. Therefore, there is a need in the art for a semiconductor structure that is formed using an SOI wafer and that has reduced harmonics and improved isolation between the active semiconductor layer and the wafer substrate.

#In view of the foregoing disclosed herein are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a deep trench isolation region extending to a fully or partially amorphized region of the SOI wafer substrate located either at the top surface of the substrate or embedded within the substrate. The deep trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can further incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.