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US 7,804,150 B2Granted
Lateral trench gate FET with direct source-drain current path
AssigneeFairchild Semiconductor Corporation
InventorsChang-ki Jeon, Gary Dolny
Life of this patent
Estimating the term…
Abstract
A field effect transistor includes a trench gate extending into a semiconductor region. The trench gate has a front wall facing a drain region and a side wall perpendicular to the front wall. A channel region extends along the side wall of the trench gate, and a drift region extends at least between the drain region and the trench gate. The drift region includes a stack of alternating conductivity type silicon layers.
Claims29
A field effect transistor (FET) comprising:
- a trench gate extending into a semiconductor region, the trench gate having a front wall facing a drain region of a first conductivity type and a side wall perpendicular to the front wall;
- a body region of a second conductivity type abutting the side wall of the trench gate;
- a source region of the first conductivity type abutting the side wall of the trench gate and extending in the body region so as to form a channel region in the body region along the side wall of the trench gate, the source region extending in a middle portion of the body region such that when the FET is in an on state, portions of a current that flows through the channel region flow in opposite directions;
- and
- a drift region extending at least between the drain region and the trench gate, the drift region comprising a stack of alternating conductivity type silicon layers.
2 more elements
A lateral field effect transistor (FET) comprising:
- a plurality of trench gates extending into a semiconductor region, the plurality of trench gates being arranged along columns, each trench gate having two active sidewalls and two non-active sidewalls, the two non-active sidewalls being perpendicular to the two active sidewalls;
- a plurality of drain regions of a first conductivity type, each drain region being located between every two adjacent columns of trench gates such that each non-active sidewall of each trench gate faces the adjacent drain region, each drain region being laterally spaced from the adjacent columns of trench gates;
- a channel region extending along each active sidewall of the plurality of trench gates such that when the lateral FET is in an on state, portions of a current that flows through the channel region flow in opposite directions;
- and
- a drift region extending between the drain regions and their adjacent columns of trench gates and between adjacent trench gates, the drift region comprising a stack of alternating conductivity type silicon layers.
2 more elements
Dependencies are inferred from the claim text.