Radiation hardened device
AssigneeIntersil Americas Inc.
InventorsStephen Joseph Gaul, Michael D. Church, Brent R. Doyle
Life of this patent
Estimating the term…
Abstract
A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.
Claims12
An integrated circuit comprising:
- a substrate;
- an oxide layer extending into the substrate and having openings to the surfaces of active regions of the substrate;
- devices formed in the active regions of the substrate;
- one of the devices having a source region and a drain region spaced in one of the active regions and self-aligned with a corresponding gate, the gate including a first gate portion and a second gate portion;
- the first gate portion extending from the oxide layer over the substrate region between the source and drain regions and defining the length of a channel region of the device;
- the second gate portion being integral to the first gate portion, extending from the oxide layer over adjacent edges of the one active region and surrounding at least the drain region with the first gate portion;
- and
- a guardring region formed in an active region, the guardring having a first electrical conductivity type and surrounding the source region, the drain region and the gate, the one active region having the first electrical conductivity type, the sources region and the drain region having a second electrical conductivity type.
An integrated circuit comprising:
- a substrate;
- an oxide layer extending into the substrate and having openings to the surface regions of the substrate;
- and
- devices formed in the openings to surface regions,
- wherein one of the devices having a source region and drain region spaced in one of the openings to the surface regions and self-aligned with a corresponding gate, the gate including a first portion extending over the opening to the surface region between the source and drain regions and defining the length of a channel region of the device and a second portion extending from the oxide layer over an adjacent edge of the opening to the surface region and defining the width of the channel region, and wherein a distance between the drain and oxide layer is greater than half the device channel length.
Dependencies are inferred from the claim text.