Buried guard ring and radiation hardened isolation structures and fabrication methods
AssigneeSilicon Space Technology Corporation
InventorWesley H. Morris
Life of this patent
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Abstract
Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
Claims41
A semiconductor device comprising:
- a source region having a first width along a first edge of a first gate electrode;
- a drain region having a second width along a second edge of the first gate electrode;
- a channel region located between the source region and the drain region, wherein the channel region has a channel length, and wherein the channel region has a third width greater than each of the first width and the second width, and forming at least one channel extension overlapping the first gate electrode, wherein the at least one channel extension provides a net channel edge length between the source region and the drain region that is greater than the channel length;
- and
- a substrate material in which the source, drain, and channel regions are formed;
- wherein the source region, the drain region, and the channel region are all formed in a bulk semiconductor substrate.
A semiconductor device comprising:
- a source region having a first width along a first edge of a first gate electrode;
- a drain region having a second width along a second edge of the first gate electrode;
- a channel region located between the source region and the drain region, wherein the channel region has a channel length, and wherein the channel region has a third width greater than each of the first width and the second width, and forming at least one channel extension overlapping the first gate electrode, wherein the at least one channel extension provides a net channel edge length between the source region and the drain region that is greater than the channel length;
- and
- a substrate material in which the source, drain, and channel regions are formed;
- wherein the source region, the drain region, and the channel region are all formed in an epitaxial layer formed on a semiconductor substrate, wherein the epitaxial layer and the semiconductor substrate have a first conductivity type, and wherein an impurity concentration of the epitaxial layer is less than an impurity concentration of the semiconductor substrate.
A semiconductor device comprising:
- a source region having a first width along a first edge of a first gate electrode;
- a drain region having a second width along a second edge of the first gate electrode;
- a channel region located between the source region and the drain region, wherein the channel region has a channel length, and wherein the channel region has a third width greater than each of the first width and the second width, and forming at least one channel extension overlapping the first gate electrode, wherein the at least one channel extension provides a net channel edge length between the source region and the drain region that is greater than the channel length;
- a substrate material in which the source, drain, and channel regions are formed, wherein the substrate material has a first conductivity type;
- and
- a buried layer having the first conductivity type and located beneath the source, drain, and channel regions, wherein the buried layer extends substantially continuously beneath the source, drain, and channel regions, and wherein a buried layer impurity concentration is greater than an impurity concentration of the substrate.
Dependencies are inferred from the claim text.