Method of forming nitride films with high compressive stress for improved PFET device performance

#This invention relates to the manufacture of advanced semiconductor devices, and particularly to improving charge mobility in high performance p-type field effect transistors (PFETs) in CMOS integrated devices.

#In the field of semiconductor device design, it is known that mechanical stresses within the device substrate can affect device performance. Stress engineering has come to play an important role in improving the performance of semiconductor devices. In the case of field-effect transistors (FETs), stress is applied to the channel region of the FET to cause increased mobility of electrons or holes, which in turn gives a substantial improvement in device speed. In a typical CMOS integrated circuit device, both n-type and p-type FETs (NFETs and PFETs respectively) are used. The stress components for the NFET and PFET in a given device must be engineered and applied differently, in accordance with the type of device and whether the direction is longitudinal (on the same axis as the channel current) or transverse to the channel current. It is known that the best stress design provides tensile stress in both longitudinal and transverse directions in the channel region under the gate of the NFET, but longitudinal compressive stress and transverse tensile stress in the channel region under the gate of the PFET.

#FIGS. 1A and 1B schematically illustrate a typical device with the desired stress arrangement. FIG. 1A is a cross-section view of NFET and PFET gate structures 10, 20 formed on substrate 1 with an isolation region 15 (generally shallow-trench isolation or STI) between them. The NFET and PFET gate materials 11, 21 have channel regions 13, 23 beneath them. FIG. 1B is a plan view of the channel regions with the desired stresses, where arrows T and C represent tensile stress and compressive stress respectively.

#FIG. 1A is a schematic illustration in cross-section view of a typical CMOS device having NFET and PFET gate structures.

#FIG. 1B is a schematic illustration in plan view of the gate channels in FIG. 1A, showing the desired longitudinal stress in the NFET and PFET respectively.

#FIG. 2 shows an HDP nitride layer deposited on the PFET structure, in accordance with an embodiment of the invention.

#In a preferred embodiment of the invention, a nitride film is deposited on a substrate having a PFET device using a high-density plasma (HDP) process. In particular, the HDP nitride deposition process includes high frequency bias power.

#The HDP nitride film 25 is deposited over the substrate 1 on which NFET and PFET gate structures 10, 20 have been formed, as shown in FIG. 2. The NFET gate structure is covered with a blocking layer 24 (e.g. photoresist) before the compressive nitride film is deposited, so that the nitride contacts the PFET only. A typical thickness for the nitride film 25 is in the range 300-2000 Å. The blocking layer is subsequently removed by any convenient process, so that compressive stress is applied to the PFET gate structures but not the NFET gate structures.

#The processes described below have been implemented in a Novellus Speed HDP chemical vapor deposition tool from Novellus Systems, Inc. Argon, silane and nitrogen are used as precursor gases, with flow rates typically 350 sccm, 150 sccm and 600 sccm respectively when 200 mm substrates are used, and 230 sccm, 90 sccm and 310 sccm respectively when 300 mm substrates are used. During the deposition process the substrate temperature is about 375-400° C. and the gas pressure is less than 10 mTorr. The low frequency (LF) power is in the range 1000-2000 W for 200 mm substrates and in the range 2500-4000 W for 300 mm substrates. The high frequency (HF) bias power is in the range 50-150 W when 200 mm substrates are used, and in the range 300-500 W when 300 mm substrates are used. Table 1 shows results of HDP nitride deposition on five 200 mm wafers with Ar, SiH4 and N2 flow rates as given above, with a total power of 1870 watts.