US 7,804,122 B2Granted

Non-volatile memory

AssigneeMacronix International Co., Ltd.

InventorsChin-Hsien Chen, Ying-Tso Chen, Chien-Hung Liu, Shou-Wei Huang

Life of this patent

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Abstract

A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.

Claims9

Dependent claims

A non-volatile memory, comprising:

a substrate, having two openings;
a stacked gate structure, disposed on the substrate between the two openings, wherein the stacked gate structure comprises a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer sequentially stacked on the substrate;
a liner, disposed on a bottom of each of the two openings and a portion of a sidewall of each of the two openings, wherein a top surface of the liner is lower than that of the substrate;
a second conductive layer, disposed on the liner at the bottom of each of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner;
and
a third conductive layer, disposed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is higher than a top surface of the substrate and lower than that of the first dielectric layer.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/434,828Filed 4 May 2009 · division
Priority: 16 May 2006
Published: US 2009/0212353 A127 Aug 2009
Granted: 28 Sep 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
H10D 30/681
Floating-gate IGFETs: having only two programming levels

Family

Application11/435,458Parent of this division · filed 16 May 2006
US 2009/0212353 A1Pre-grant publication · published 27 Aug 2009
US 7,572,691 B2Parent of this division
US 2007/0269943 A1Published application
US 7,804,122 B2This patent

From the US filing history. Foreign family members aren’t listed.