Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same

A semiconductor integrated circuit device comprising:

• a semiconductor substrate having a main surface;
• a first MISFET arranged at a first circuit forming region of the main surface and constituting a first circuit, the first MISFET including a source region and a drain region each formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode;
• a second MISFET arranged at a logic circuit forming region of the main surface and constituting a second circuit different from the first circuit, the second MISFET including a source region and a drain region each formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode;
• a first capacitor element having a lower electrode, a first insulating film formed on the lower electrode, a higher electrode formed on the first insulating film, such that the higher electrode is formed over the semiconductor substrate;
• a second insulating film formed over the first MISFET, the second MISFET and the first capacitor element;
• and
• a second capacitor element arranged at the first circuit forming region and formed over the second insulating film, the second capacitor element having a lower electrode formed over the second insulating film, a third insulating film formed on the lower electrode, and a higher electrode formed on the third insulating film.