Solid-state imaging device
AssigneeSony Corporation
InventorsTakashi Abe, Ryoji Suzuki, Keiji Mabuchi, Testuya Iizuka, Takahisa Ueno, Tsutomu Haruta
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AssigneeSony Corporation
InventorsTakashi Abe, Ryoji Suzuki, Keiji Mabuchi, Testuya Iizuka, Takahisa Ueno, Tsutomu Haruta
Estimating the term…
A solid-state imaging device having an arrangement in which well contact is achieved for each pixel is provided. In the solid-state imaging device, a well contact part is formed in an activation region of a photoelectric conversion portion. The well contact part fixes a well in which the photoelectric conversion portion and transistors of the pixel are provided at a predetermined potential.
A solid-state imaging device comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
Constructional details of image sensors: geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
Image sensors: complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
Constructional details of image sensors: pixels having integrated switching, control, storage or amplification elements
Solar cells and light sensors
Term ended 5 Dec 2024 (estimated)
1. Field of the Invention
The present invention relates to solid-state imaging devices, and more particularly, to a solid-state imaging device, such as a complementary metal-oxide semiconductor (CMOS) image sensor including amplifying elements for respective pixels.
2. Description of the Related Art
FIG. 1 is a block diagram schematically showing the arrangement of a CMOS image sensor according to the present invention;
FIG. 2 is a circuit diagram showing an example of the arrangement of a unit pixel;
FIG. 3 is a plan pattern view showing a pixel structure according to a first embodiment;
Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram schematically showing the arrangement of a solid-state imaging device, such as a CMOS image sensor, according to the present invention. Referring to FIG. 1, a pixel array area 11, a vertical driving circuit 12, a shutter driving circuit 13, a correlated double sampling (CDS) circuit 14, a horizontal driving circuit 15, an automatic gain control (AGC) circuit 16, an analog/digital (A/D) conversion circuit 17, a timing generator 18, and the like are integrated on a substrate (chip) 19. Hereinafter, a semiconductor chip including the pixel array area 11 and the peripheral driving circuits 12 to 18 mounted on the chip 19 is referred to as a sensor chip 10.
The pixel array area 11 includes pixels arranged in a two-dimensional array fashion. Each of the pixels includes one or more photoelectric conversion portions. A pixel output line for outputting signals of the pixels and various control lines for driving the pixels are arranged so as to correspond to the arrangement of the pixels. Each of the pixels includes at least a photoelectric conversion portion for photo-electrically converting incident light to be accumulated, a reading portion for reading a signal charge from the photoelectric conversion portion to a floating doped region, a reset portion for resetting the floating doped region, and an amplifying portion for amplifying the signal charge read to the floating doped region. A specific example of a circuit of a pixel of this type will be described below.