Semiconductor device and method for adjusting characteristics thereof

A semiconductor device comprising:

• a signal-transmission interconnection for transmitting signals;
• a MOS capacitance element having a source, a drain, a well, and a gate electrode connected to said signal-transmission interconnection;
• a first voltage-applying interconnection being connected to said source and said drain of said MOS capacitance element, and said first voltage-applying interconnection being configured to apply a voltage to said source and said drain of said MOS capacitance element;
• a second voltage-applying interconnection being connected to said well of said MOS capacitance element, and said second voltage-applying interconnection being configured to apply a voltage to said well of said MOS capacitance element;
• a ground interconnection;
• a first capacitance element for connecting said ground interconnection and said first voltage-applying interconnection;
• and
• a second capacitance element for connecting said ground interconnection and said second voltage-applying interconnection.

A semiconductor device comprising:

• a signal-transmission interconnection for transmitting signals;
• a CMOS capacitance element including (i) a n-type MOS capacitance element having source, a drain, a well, and a gate electrode connected to said signal-transmission interconnection, and
• (ii) a p-type MOS capacitance element having a source, a drain, a well, and a gate electrode connected to said signal-transmission interconnection;
• a first voltage-applying interconnection being connected to said source and said drain of said n-type MOS capacitance element, and said first voltage-applying interconnection being configured to apply a voltage to said source and said drain of said n-type MOS capacitance element;
• a second voltage-applying interconnection being connected to said well of said n-type MOS capacitance element, and said second voltage-applying interconnection being configured to apply a voltage to said well of said n-type MOS capacitance element;
• a third voltage-applying interconnection being connected to said source and said drain of said p-type MOS capacitance element, and said third voltage-applying interconnection being configured to apply a voltage to said source and said drain of said p-type MOS capacitance element;
• and
• a fourth voltage-applying interconnection being connected to said well of said p-type MOS capacitance element, and said fourth voltage-applying interconnection being configured to apply a voltage to said well of said p-type MOS capacitance element.

A semiconductor device comprising:

• a signal-transmission interconnection for transmitting signals;
• first and second MOS capacitance elements, each MOS capacitance element having a source, a drain, a well, and a gate electrode, said gate electrode for said first MOS capacitance element being connected at a different position from said gate electrode for said second MOS capacitance element in the line length direction of said signal-transmission interconnection, along said signal-transmission interconnection;
• a first voltage-applying interconnection being connected to said source and said drain of said first MOS capacitance element, and said first voltage-applying interconnection being configured to a voltage to said source and said drain of said first MOS capacitance element;
• a second voltage-applying interconnection being connected to said well of said first MOS capacitance element, and said second voltage-applying interconnection being configured to apply a voltage to said well of said first MOS capacitance element;
• a third voltage-applying interconnection being connected to said source and said drain of said second MOS capacitance element, and said third voltage-applying interconnection being configured to apply a voltage to said source and said drain of said second MOS capacitance element;
• and
• a fourth voltage-applying interconnection being connected to said well of said second MOS capacitance element, and said fourth voltage-applying interconnection being configured to apply a voltage to said well of said second MOS capacitance element,
• wherein the voltages of said first, second, third and fourth voltage-applying interconnections are controlled independently from each other.

A semiconductor device comprising:

• a first signal-transmission interconnection for transmitting a first signal;
• a second signal-transmission interconnection for transmitting a second signal, the second signal being an inverted signal of the first signal and said second signal-transmission interconnection being arranged substantially parallel to said first signal-transmission interconnection;
• a first MOS capacitance element having a source, a drain, a well, and a gate electrode connected to said first signal-transmission interconnection;
• a second MOS capacitance element having a source, a drain, a well, and a gate electrode connected to said second signal-transmission interconnection;
• a first voltage-applying interconnection being connected to said source and said drain of said first MOS capacitance element, and said source and said drain of said second MOS capacitance element, and said first voltage-applying interconnection being configured to apply a voltage to said sources and said drains of said first MOS capacitance element and said second MOS capacitance element;
• and
• a second voltage-applying interconnection being connected to said well of said first MOS capacitance element and said well of said second MOS capacitance element, and said second voltage-applying interconnection being configured to apply a voltage to said well of said first MOS capacitance element and said well of said second MOS capacitance element.